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Message-ID: <CAE-0n52mEy1GReYwcVrffT2KOy4EHMHH-RyCJ_mmxhaeXwGdYA@mail.gmail.com>
Date: Mon, 26 Jul 2021 20:16:41 -0400
From: Stephen Boyd <swboyd@...omium.org>
To: Akhil P Oommen <akhilpo@...eaurora.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
<devicetree@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
dri-devel@...ts.freedesktop.org,
freedreno <freedreno@...ts.freedesktop.org>,
linux-arm-msm@...r.kernel.org
Cc: Jonathan Marek <jonathan@...ek.ca>,
Douglas Anderson <dianders@...omium.org>,
Jordan Crouse <jordan@...micpenguin.net>,
Matthias Kaehlcke <mka@...omium.org>,
Rob Clark <robdclark@...il.com>,
Andy Gross <agross@...nel.org>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] arm64: dts: qcom: sc7280: Add gpu support
Quoting Akhil P Oommen (2021-07-24 10:29:00)
> Add the necessary dt nodes for gpu support in sc7280.
>
> Signed-off-by: Akhil P Oommen <akhilpo@...eaurora.org>
> ---
> This patch has dependency on the GPUCC bindings patch here:
> https://patchwork.kernel.org/project/linux-arm-msm/patch/1619519590-3019-4-git-send-email-tdas@codeaurora.org/
To avoid the dependency the plain numbers can be used.
>
> Changes in v2:
> - formatting update and removed a duplicate header (Stephan)
>
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 116 +++++++++++++++++++++++++++++++++++
> 1 file changed, 116 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 029723a..524a5e0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -585,6 +586,121 @@
> #clock-cells = <1>;
> };
>
> + gpu@...0000 {
> + compatible = "qcom,adreno-635.0", "qcom,adreno";
> + #stream-id-cells = <16>;
> + reg = <0 0x03d00000 0 0x40000>,
> + <0 0x03d9e000 0 0x1000>,
> + <0 0x03d61000 0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&adreno_smmu 0 0x401>;
> + operating-points-v2 = <&gpu_opp_table>;
> + qcom,gmu = <&gmu>;
> + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
> + interconnect-names = "gfx-mem";
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-550000000 {
> + opp-hz = /bits/ 64 <550000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <6832000>;
> + };
> +
> + opp-450000000 {
> + opp-hz = /bits/ 64 <450000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + opp-peak-kBps = <4068000>;
> + };
> +
> + opp-315000000 {
> + opp-hz = /bits/ 64 <315000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + opp-peak-kBps = <1804000>;
> + };
> + };
> + };
> +
> + gmu: gmu@...9000 {
> + compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
> + reg = <0 0x03d6a000 0 0x34000>,
> + <0 0x3de0000 0 0x10000>,
> + <0 0x0b290000 0 0x10000>;
> + reg-names = "gmu", "rscc", "gmu_pdc";
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hfi", "gmu";
> + clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
> + clock-names = "gmu",
> + "cxo",
> + "axi",
> + "memnoc",
> + "ahb",
> + "hub",
> + "smmu_vote";
> + power-domains = <&gpucc GPU_CC_CX_GDSC>,
> + <&gpucc GPU_CC_GX_GDSC>;
> + power-domain-names = "cx",
> + "gx";
> + iommus = <&adreno_smmu 5 0x400>;
> + operating-points-v2 = <&gmu_opp_table>;
> +
> + gmu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-200000000 {
> + opp-hz = /bits/ 64 <200000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> + };
> + };
> +
> + adreno_smmu: iommu@...0000 {
> + compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
> + reg = <0 0x03da0000 0 0x20000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <2>;
> + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
> + <&gpucc GPU_CC_AHB_CLK>,
> + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
> + <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_HUB_CX_INT_CLK>,
> + <&gpucc GPU_CC_HUB_AON_CLK>;
> + clock-names = "gcc_gpu_memnoc_gfx_clk",
> + "gcc_gpu_snoc_dvm_gfx_clk",
> + "gpu_cc_ahb_clk",
> + "gpu_cc_hlos1_vote_gpu_smmu_clk",
> + "gpu_cc_cx_gmu_clk",
> + "gpu_cc_hub_cx_int_clk",
> + "gpu_cc_hub_aon_clk";
> +
> + power-domains = <&gpucc GPU_CC_CX_GDSC>;
> + };
> +
> lpass_ag_noc: interconnect@...0000 {
This node is 3c40000 and the one above is 3da0000. 3c comes before 3d.
Please order nodes properly.
> reg = <0 0x03c40000 0 0xf080>;
> compatible = "qcom,sc7280-lpass-ag-noc";
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