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Message-ID: <20210727055644.yqwskkr4htcmwzem@pengutronix.de>
Date: Tue, 27 Jul 2021 07:56:44 +0200
From: Oleksij Rempel <o.rempel@...gutronix.de>
To: alexandru.tachici@...log.com
Cc: netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, robh+dt@...nel.org, andrew@...n.ch,
hkallweit1@...il.com, linux@...linux.org.uk, davem@...emloft.net,
kuba@...nel.org
Subject: Re: [PATCH v2 1/7] ethtool: Add 10base-T1L link mode entries
On Mon, Jul 12, 2021 at 04:06:25PM +0300, alexandru.tachici@...log.com wrote:
> From: Alexandru Tachici <alexandru.tachici@...log.com>
>
> Add entries for the 10base-T1L full and half duplex supported modes.
>
> Signed-off-by: Alexandru Tachici <alexandru.tachici@...log.com>
> ---
> drivers/net/phy/phy-core.c | 4 +++-
> include/uapi/linux/ethtool.h | 2 ++
> net/ethtool/common.c | 2 ++
> 3 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
> index 2870c33b8975..fd9c83ce10fc 100644
> --- a/drivers/net/phy/phy-core.c
> +++ b/drivers/net/phy/phy-core.c
> @@ -13,7 +13,7 @@
> */
> const char *phy_speed_to_str(int speed)
> {
> - BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92,
> + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 94,
> "Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
> "If a speed or mode has been added please update phy_speed_to_str "
> "and the PHY settings array.\n");
> @@ -176,6 +176,8 @@ static const struct phy_setting settings[] = {
> /* 10M */
> PHY_SETTING( 10, FULL, 10baseT_Full ),
> PHY_SETTING( 10, HALF, 10baseT_Half ),
> + PHY_SETTING( 10, FULL, 10baseT1L_Full ),
> + PHY_SETTING( 10, HALF, 10baseT1L_Half ),
> };
> #undef PHY_SETTING
IEEE 802.3cg-2019 do not define half duplex support for T1L, only for
T1S. IMO, 10baseT1L_Half can be dropped.
> diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h
> index 67aa7134b301..8a905466d7dc 100644
> --- a/include/uapi/linux/ethtool.h
> +++ b/include/uapi/linux/ethtool.h
> @@ -1659,6 +1659,8 @@ enum ethtool_link_mode_bit_indices {
> ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89,
> ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
> ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
> + ETHTOOL_LINK_MODE_10baseT1L_Half_BIT = 92,
> + ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 93,
> /* must be last entry */
> __ETHTOOL_LINK_MODE_MASK_NBITS
> };
> diff --git a/net/ethtool/common.c b/net/ethtool/common.c
> index f9dcbad84788..5b93d888fd83 100644
> --- a/net/ethtool/common.c
> +++ b/net/ethtool/common.c
> @@ -199,6 +199,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
> __DEFINE_LINK_MODE_NAME(400000, CR4, Full),
> __DEFINE_LINK_MODE_NAME(100, FX, Half),
> __DEFINE_LINK_MODE_NAME(100, FX, Full),
> + __DEFINE_LINK_MODE_NAME(10, T1L, Half),
> + __DEFINE_LINK_MODE_NAME(10, T1L, Full),
> };
> static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
>
> --
> 2.25.1
>
>
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