linux-kernel - [PATCH v2 2/8] clk: rockchip: fix clk-pll rk356x early pll init

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20210728180034.717953-3-pgwipeout@gmail.com>
Date:   Wed, 28 Jul 2021 14:00:28 -0400
From:   Peter Geis <pgwipeout@...il.com>
To:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Heiko Stuebner <heiko@...ech.de>
Cc:     Peter Geis <pgwipeout@...il.com>, linux-clk@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2 2/8] clk: rockchip: fix clk-pll rk356x early pll init

The rk356x needs to reclock certain plls at boot. If the grf phandles
are not linked in the cru and pmucru nodes, it is unable to apply any
assigned-clock-rates at boot.

Fix this by removing the check for the grf for selecting the utilized
operations.

"The rk3568 reuses the pll_rk3328-type which in turn is a modified
pll_rk3036 and uses their ops. Which in turn means the pll shouldn't
access the GRF at all, as it uses the pll's own register to check the
locked state."

Suggested-by: Heiko Stuebner <heiko@...ech.de>
Link:
https://lore.kernel.org/linux-devicetree/20210728135534.703028-7-pgwipeout@gmail.com/
Fixes: c9c3c6eecc55 ("clk: rockchip: simplify GRF handling in pll
clocks")
Signed-off-by: Peter Geis <pgwipeout@...il.com>
---
 drivers/clk/rockchip/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index fe937bcdb487..f7827b3b7fc1 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -940,7 +940,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
 	switch (pll_type) {
 	case pll_rk3036:
 	case pll_rk3328:
-		if (!pll->rate_table || IS_ERR(ctx->grf))
+		if (!pll->rate_table)
 			init.ops = &rockchip_rk3036_pll_clk_norate_ops;
 		else
 			init.ops = &rockchip_rk3036_pll_clk_ops;
-- 
2.25.1