lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <d96880c4-75ab-50b5-3ecf-0dfd2aa3b8f3@socionext.com>
Date:   Wed, 28 Jul 2021 14:29:15 +0900
From:   Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Pali Rohár <pali@...nel.org>
Cc:     Bjorn Helgaas <helgaas@...nel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Rob Herring <robh@...nel.org>,
        Jingoo Han <jingoohan1@...il.com>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Marc Zyngier <maz@...nel.org>, linux-pci@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Jassi Brar <jaswinder.singh@...aro.org>,
        Masami Hiramatsu <masami.hiramatsu@...aro.org>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v8 3/3] PCI: uniphier: Add misc interrupt handler to
 invoke PME and AER

Hi Lorenzo, Pali,

On 2021/07/23 18:36, Kunihiko Hayashi wrote:
> Hi Pali,

[snip]

>> Just you need to specify that new/private IRQ domain into
>> irq_find_mapping() call.
> 
> I'll try to replace the events with new IRQ domain.
According to Pali's suggestion, the bridge handles INTX and it isn't difficult
to change IRQ's map for Root Port like the example.
It seems that it can't be applied to MSI.

On the other hand, according to Lorenzo's suggestion,

 >>>>>>> IMO this should be modelled with a separate IRQ domain and chip for
 >>>>>>> the root port (yes this implies describing the root port in the dts
 >>>>>>> file with a separate msi-parent).

Interrupts for PME/AER event is assigned to number 0 of MSI IRQ domain.
(pcie_port_enable_irq_vec() in portdrv_core.c)
This expects MSI status bit 0 to be set when the event occurs.

However, in the uniphier PCIe controller, MSI status bit 0 is not set, but
the PME/AER status bit in the glue logic is set.

I think that it's hard to associate the new domain and "MSI-IRQ 0" event
if the new IRQ domain and chip is modelled.
So, I have no idea to handle both new IRQ domain and cascaded MSI event.
Is there any example for that?

Thank you,

---
Best Regards
Kunihiko Hayashi

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ