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Message-Id: <1627581885-32165-2-git-send-email-sibis@codeaurora.org>
Date: Thu, 29 Jul 2021 23:34:42 +0530
From: Sibi Sankar <sibis@...eaurora.org>
To: sboyd@...nel.org, bjorn.andersson@...aro.org, robh+dt@...nel.org,
mka@...omium.org
Cc: viresh.kumar@...aro.org, agross@...nel.org, rjw@...ysocki.net,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
dianders@...omium.org, tdas@...eaurora.org,
Sibi Sankar <sibis@...eaurora.org>
Subject: [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350
Re-arranging the register regions to support per core L3 DCVS would lead
to bindings breakage when using an older dt with a newer kernel. So,
document the EPSS compatible for SM8250/SM8350 SoCs and use them in the
CPUFreq-hw driver to prevent such breakages.
Signed-off-by: Sibi Sankar <sibis@...eaurora.org>
---
Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
index 9299028ee712..ee52fd8d3c9a 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
@@ -8,7 +8,11 @@ Properties:
- compatible
Usage: required
Value type: <string>
- Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
+ Definition: must be one of:
+ "qcom,cpufreq-epss"
+ "qcom,cpufreq-hw"
+ "qcom,sm8250-cpufreq-epss"
+ "qcom,sm8350-cpufreq-epss"
- clocks
Usage: required
--
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