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Message-Id: <20210730134552.853350-4-bert@biot.com>
Date: Fri, 30 Jul 2021 15:45:50 +0200
From: Bert Vermeulen <bert@...t.com>
To: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>,
soc@...nel.org, Rob Herring <robh+dt@...nel.org>
Cc: Bert Vermeulen <bert@...t.com>, John Crispin <john@...ozen.org>,
Felix Fietkau <nbd@....name>
Subject: [PATCH 3/5] ARM: dts: Add basic support for EcoNet EN7523
From: John Crispin <john@...ozen.org>
Add basic support for EcoNet EN7523, enough for booting to console.
The UART is basically 8250-compatible, except for the clock selection.
A clock-frequency value is synthesized to get this to run at 115200 bps.
Signed-off-by: John Crispin <john@...ozen.org>
Signed-off-by: Bert Vermeulen <bert@...t.com>
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/en7523-evb.dts | 17 ++++
arch/arm/boot/dts/en7523.dtsi | 128 +++++++++++++++++++++++++++++++
3 files changed, 147 insertions(+)
create mode 100644 arch/arm/boot/dts/en7523-evb.dts
create mode 100644 arch/arm/boot/dts/en7523.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 863347b6b65e..3eeb7715c6ce 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -174,6 +174,8 @@ dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-lego-ev3.dtb
dtb-$(CONFIG_ARCH_DIGICOLOR) += \
cx92755_equinox.dtb
+dtb-$(CONFIG_ARCH_ECONET) += \
+ en7523-evb.dtb
dtb-$(CONFIG_ARCH_EXYNOS3) += \
exynos3250-artik5-eval.dtb \
exynos3250-monk.dtb \
diff --git a/arch/arm/boot/dts/en7523-evb.dts b/arch/arm/boot/dts/en7523-evb.dts
new file mode 100644
index 000000000000..c5b75eb3715e
--- /dev/null
+++ b/arch/arm/boot/dts/en7523-evb.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "en7523.dtsi"
+
+/ {
+ model = "Econet EN7523 Evaluation Board";
+ compatible = "econet,en7523-evb", "econet,en7523";
+
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon=uart8250,mmio32,0x1fbf0000 console=ttyS0,115200";
+ stdout-path = "serial0:115200n8";
+ };
+};
diff --git a/arch/arm/boot/dts/en7523.dtsi b/arch/arm/boot/dts/en7523.dtsi
new file mode 100644
index 000000000000..f4fe1c6f66e8
--- /dev/null
+++ b/arch/arm/boot/dts/en7523.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ npu_binary@...00000 {
+ no-map;
+ reg = <0x84000000 0xA00000>;
+ };
+
+ npu_flag@...0000 {
+ no-map;
+ reg = <0x84B00000 0x100000>;
+ };
+
+ npu_pkt@...00000 {
+ no-map;
+ reg = <0x85000000 0x1A00000>;
+ };
+
+ npu_phyaddr@...00000 {
+ no-map;
+ reg = <0x86B00000 0x100000>;
+ };
+
+ npu_rxdesc@...00000 {
+ no-map;
+ reg = <0x86D00000 0x100000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&L2_0>;
+
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ enable-method = "psci";
+ clock-frequency = <80000000>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ gic: interrupt-controller@...00000 {
+ compatible = "arm,gic-v3";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x09000000 0x20000>,
+ <0x09080000 0x80000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+ its: gic-its@...20000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cell = <1>;
+ reg = <0x090200000 0x20000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <25000000>;
+ };
+
+ memory@...00000 {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ uart1: serial@...f0000 {
+ compatible = "ns8250";
+ reg = <0x1fbf0000 0x30>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <1843200>;
+ status = "okay";
+ };
+};
--
2.25.1
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