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Message-ID: <YQhGRB3wBgQ1Kw9E@google.com>
Date: Mon, 2 Aug 2021 12:23:48 -0700
From: Matthias Kaehlcke <mka@...omium.org>
To: Prasad Malisetty <pmaliset@...eaurora.org>
Cc: agross@...nel.org, bjorn.andersson@...aro.org, bhelgaas@...gle.com,
robh+dt@...nel.org, swboyd@...omium.org, lorenzo.pieralisi@....com,
svarbanov@...sol.com, devicetree@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-usb@...r.kernel.org,
linux-kernel@...r.kernel.org, dianders@...omium.org,
vbadigan@...eaurora.org, sallenki@...eaurora.org
Subject: Re: [PATCH v4 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY
related nodes
On Fri, Jul 16, 2021 at 07:28:45PM +0530, Prasad Malisetty wrote:
> Add PCIe controller and PHY nodes for sc7280 SOC.
>
> Signed-off-by: Prasad Malisetty <pmaliset@...eaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 125 +++++++++++++++++++++++++++++++++++
> 1 file changed, 125 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index a8c274a..06baf88 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -15,6 +15,7 @@
> #include <dt-bindings/reset/qcom,sdm845-pdc.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> #include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/gpio/gpio.h>
>
> / {
> interrupt-parent = <&intc>;
> @@ -546,6 +547,118 @@
> #power-domain-cells = <1>;
> };
>
> + pcie1: pci@...8000 {
> + compatible = "qcom,pcie-sc7280", "qcom,pcie-sm8250", "snps,dw-pcie";
> + reg = <0 0x01c08000 0 0x3000>,
> + <0 0x40000000 0 0xf1d>,
> + <0 0x40000f20 0 0xa8>,
> + <0 0x40001000 0 0x1000>,
> + <0 0x40100000 0 0x100000>;
> +
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + device_type = "pci";
> + linux,pci-domain = <1>;
> + bus-range = <0x00 0xff>;
> + num-lanes = <2>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
> +
> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
> + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
> + <&pcie1_lane 0>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_PCIE_1_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
> + <&gcc GCC_DDRSS_PCIE_SF_CLK>;
> +
> + clock-names = "pipe",
> + "pipe_mux",
> + "phy_pipe",
> + "ref",
> + "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "tbu",
> + "ddrss_sf_tbu";
> +
> + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + resets = <&gcc GCC_PCIE_1_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc GCC_PCIE_1_GDSC>;
> +
> + phys = <&pcie1_lane>;
> + phy-names = "pciephy";
> +
> + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie1_default_state>;
> +
> + iommus = <&apps_smmu 0x1c80 0x1>;
> +
> + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
> + <0x100 &apps_smmu 0x1c81 0x1>;
> +
> + status = "disabled";
> + };
> +
> + pcie1_phy: phy@...e000 {
> + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
> + reg = <0 0x01c0e000 0 0x1c0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_CLKREF_EN>,
> + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "refgen";
> +
> + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
> + reset-names = "phy";
> +
> + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + status = "disabled";
> +
> + pcie1_lane: lanes@...e200 {
> + reg = <0 0x01c0e200 0 0x170>,
> + <0 0x01c0e400 0 0x200>,
> + <0 0x01c0ea00 0 0x1f0>,
> + <0 0x01c0e600 0 0x170>,
> + <0 0x01c0e800 0 0x200>,
> + <0 0x01c0ee00 0 0xf4>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "pipe0";
> +
> + #phy-cells = <0>;
> + #clock-cells = <1>;
> + clock-output-names = "pcie_1_pipe_clk";
> + };
> + };
> +
> stm@...2000 {
> compatible = "arm,coresight-stm", "arm,primecell";
> reg = <0 0x06002000 0 0x1000>,
> @@ -1185,6 +1298,18 @@
> pins = "gpio46", "gpio47";
> function = "qup13";
> };
> +
> + pcie1_default_state: pcie1-default-state {
> + clkreq {
> + pins = "gpio79";
> + function = "pcie1_clkreqn";
> + };
> +
> + wake-n {
> + pins = "gpio3";
> + function = "gpio";
> + };
This could be essentially any GPIO, right? Does it really make sense to
have this node in the SoC file? I would say it belongs in the board file.
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