linux-kernel - Re: [PATCH v3 09/13] ARM: dts: sti: update clkgen-fsyn entries in stih418-clock

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Date:   Tue, 3 Aug 2021 14:07:40 +0200
From:   Patrice CHOTARD <patrice.chotard@...s.st.com>
To:     Alain Volmat <avolmat@...com>, Rob Herring <robh+dt@...nel.org>
CC:     Arnd Bergmann <arnd@...db.de>,
        <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 09/13] ARM: dts: sti: update clkgen-fsyn entries in
 stih418-clock

Hi Alain

On 3/31/21 10:42 PM, Alain Volmat wrote:
> The clkgen-fsyn driver now embed the clock names (assuming the
> right compatible is used). Remove all clock-output-names property
> and update when necessary the compatible.
> 
> Signed-off-by: Alain Volmat <avolmat@...com>
> ---
>  arch/arm/boot/dts/stih418-clock.dtsi | 26 +++-----------------------
>  1 file changed, 3 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi
> index d628e656458d..e84c476b83ed 100644
> --- a/arch/arm/boot/dts/stih418-clock.dtsi
> +++ b/arch/arm/boot/dts/stih418-clock.dtsi
> @@ -94,11 +94,6 @@
>  			reg = <0x9103000 0x1000>;
>  
>  			clocks = <&clk_sysin>;
> -
> -			clock-output-names = "clk-s-c0-fs0-ch0",
> -					     "clk-s-c0-fs0-ch1",
> -					     "clk-s-c0-fs0-ch2",
> -					     "clk-s-c0-fs0-ch3";
>  		};
>  
>  		clk_s_c0: clockgen-c@...3000 {
> @@ -150,15 +145,10 @@
>  
>  		clk_s_d0_quadfs: clk-s-d0-quadfs@...4000 {
>  			#clock-cells = <1>;
> -			compatible = "st,quadfs";
> +			compatible = "st,quadfs-d0";
>  			reg = <0x9104000 0x1000>;
>  
>  			clocks = <&clk_sysin>;
> -
> -			clock-output-names = "clk-s-d0-fs0-ch0",
> -					     "clk-s-d0-fs0-ch1",
> -					     "clk-s-d0-fs0-ch2",
> -					     "clk-s-d0-fs0-ch3";
>  		};
>  
>  		clockgen-d0@...4000 {
> @@ -179,15 +169,10 @@
>  
>  		clk_s_d2_quadfs: clk-s-d2-quadfs@...6000 {
>  			#clock-cells = <1>;
> -			compatible = "st,quadfs";
> +			compatible = "st,quadfs-d2";
>  			reg = <0x9106000 0x1000>;
>  
>  			clocks = <&clk_sysin>;
> -
> -			clock-output-names = "clk-s-d2-fs0-ch0",
> -					     "clk-s-d2-fs0-ch1",
> -					     "clk-s-d2-fs0-ch2",
> -					     "clk-s-d2-fs0-ch3";
>  		};
>  
>  		clockgen-d2@...6000 {
> @@ -210,15 +195,10 @@
>  
>  		clk_s_d3_quadfs: clk-s-d3-quadfs@...7000 {
>  			#clock-cells = <1>;
> -			compatible = "st,quadfs";
> +			compatible = "st,quadfs-d3";
>  			reg = <0x9107000 0x1000>;
>  
>  			clocks = <&clk_sysin>;
> -
> -			clock-output-names = "clk-s-d3-fs0-ch0",
> -					     "clk-s-d3-fs0-ch1",
> -					     "clk-s-d3-fs0-ch2",
> -					     "clk-s-d3-fs0-ch3";
>  		};
>  
>  		clockgen-d3@...7000 {
> 
Reviewed-by: Patrice Chotard <patrice.chotard@...s.st.com>

Thanks
Patrice