linux-kernel - Re: [PATCH v5 11/12] x86/tdx: Don't write CSTAR MSR on Intel

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <2f2f0bfa-4881-81dc-65a3-1e5c7cbf85c0@intel.com>
Date:   Wed, 4 Aug 2021 14:48:36 -0700
From:   Dave Hansen <dave.hansen@...el.com>
To:     "Kuppuswamy, Sathyanarayanan" 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>,
        Sean Christopherson <seanjc@...gle.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        Peter Zijlstra <peterz@...radead.org>,
        Andy Lutomirski <luto@...nel.org>,
        Peter H Anvin <hpa@...or.com>,
        Tony Luck <tony.luck@...el.com>,
        Dan Williams <dan.j.williams@...el.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Kirill Shutemov <kirill.shutemov@...ux.intel.com>,
        Kuppuswamy Sathyanarayanan <knsathya@...nel.org>,
        x86@...nel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 11/12] x86/tdx: Don't write CSTAR MSR on Intel

On 8/4/21 2:03 PM, Kuppuswamy, Sathyanarayanan wrote:
>> Is #GP the actual TDX-Module behavior?  If so, isn't that a
>> contradiction with
> 
> No, #GP is triggered by guest.
...
>> Regardless of #GP versus #VE, "Table 16.2 MSR Virtualization" needs
>> to state the actual behavior.
> 
> Even in this case, it will trigger #VE. But since CSTAR MSR is not 
> supported, write to it will fail and leads to #VE fault.

Sathya, I think there might be a mixup of terminology here that's
confusing.  I'm confused by this exchange.

In general, we refer to hardware exceptions by their architecture names:
#GP for general protection fault, #PF for page fault, #VE for
Virtualization Exception.

Those hardware exceptions are wired up to software handlers:
#GP lands in asm_exc_general_protection
#PF ends up in exc_page_fault
#VE ends up in exc_virtualization_exception
... and more of course

But, to add to the confusion, the #VE handler
(exc_virtualization_exception()) itself calls (or did once upon a time
call) do_general_protection() when it can't handle something.
do_general_protection() is (was?) *ALSO* called by the #GP handler.

So, is that what you meant?  By "#GP is triggered by guest", you mean
that a write to the CSTAR MSR and the resulting #VE will end up being
handled in a way that is similar to how a #GP hardware exception would
have been handled?

If that's what you meant, I'm not _sure_ that's totally accurate.  Could
you elaborate on this a bit?  It also would be really handy if you were
able to adopt the terminology I talked about above.  It will really make
things less confusing.