linux-kernel - Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support

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Date:   Wed, 4 Aug 2021 17:39:38 +0300
From:   Sam Protsenko <semen.protsenko@...aro.org>
To:     Marc Zyngier <maz@...nel.org>
Cc:     Sylwester Nawrocki <s.nawrocki@...sung.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Tomasz Figa <tomasz.figa@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>,
        Jiri Slaby <jirislaby@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Charles Keepax <ckeepax@...nsource.wolfsonmicro.com>,
        Ryu Euiyoul <ryu.real@...sung.com>,
        Tom Gall <tom.gall@...aro.org>,
        Sumit Semwal <sumit.semwal@...aro.org>,
        John Stultz <john.stultz@...aro.org>,
        Amit Pundir <amit.pundir@...aro.org>,
        devicetree <devicetree@...r.kernel.org>,
        linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux Samsung SOC <linux-samsung-soc@...r.kernel.org>,
        "open list:SERIAL DRIVERS" <linux-serial@...r.kernel.org>
Subject: Re: [PATCH 12/12] arm64: dts: exynos: Add Exynos850 SoC support

Hi Marc,

On Fri, 30 Jul 2021 at 19:50, Marc Zyngier <maz@...nel.org> wrote:
>
> On 2021-07-30 15:49, Sam Protsenko wrote:
> > Samsung Exynos850 is ARMv8-based mobile-oriented SoC.
> >
> > Features:
> >  * CPU: Cortex-A55 Octa (8 cores), up to 2 GHz
> >  * Memory interface: LPDDR4/4x 2 channels (12.8 GB/s)
> >  * SD/MMC: SD 3.0, eMMC5.1 DDR 8-bit
> >  * Modem: 4G LTE, 3G, GSM/GPRS/EDGE
> >  * RF: Quad GNSS, WiFi 5 (802.11ac), Bluetooth 5.0
> >  * GPU: Mali-G52 MP1
> >  * Codec: 1080p 60fps H64, HEVC, JPEG HW Codec
> >  * Display: Full HD+ (2520x1080)@60fps LCD
> >  * Camera: 16+5MP/13+8MP ISP, MIPI CSI 4/4/2, FD, DRC
> >  * Connectivity: USB 2.0 DRD, USI (SPI/UART/I2C), HSI2C, I3C, ADC,
> > Audio
> >
> > This patch adds minimal SoC support. Particular board device tree files
> > can include exynos850.dtsi file to get SoC related nodes, and then
> > reference those nodes further as needed.
> >
> > Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
> > ---
> >  .../boot/dts/exynos/exynos850-pinctrl.dtsi    | 782 ++++++++++++++++++
> >  arch/arm64/boot/dts/exynos/exynos850-usi.dtsi |  30 +
> >  arch/arm64/boot/dts/exynos/exynos850.dtsi     | 245 ++++++
> >  3 files changed, 1057 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos850-usi.dtsi
> >  create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> > b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..4cf0a22cc6db
>
> [...]
>
> > +     gic: interrupt-controller@...00000 {
> > +             compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>
> One thing for sure, it cannot be both. And given that it is
> an A55-based SoC, it isn't either. It is more likely a GIC400.
>

Yes, it's GIC-400, thanks for pointing that out. Will fix that in v2.

> > +             #interrupt-cells = <3>;
> > +             #address-cells = <0>;
> > +             interrupt-controller;
> > +             reg = <0x0 0x12a01000 0x1000>,
> > +                   <0x0 0x12a02000 0x1000>,
>
> This is wrong. It is architecturally set to 8kB.
>

Nice catch! Actually there is an error (typo?) in SoC's TRM, saying
that Virtual Interface Control Register starts at 0x3000 offset (from
0x12a00000), where it obviously should be 0x4000, that's probably
where this dts error originates from. Btw, I'm also seeing the same
error in exynos7.dtsi. Though I don't have a TRM for Exynos7 SoCs, so
not sure if I should go ahead and fix that too. Anyway, for Exynos850,
I'll fix that in v2 series.

> > +                   <0x0 0x12a04000 0x2000>,
> > +                   <0x0 0x12a06000 0x2000>;
> > +             interrupts = <GIC_PPI 9
> > +                             (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>
> 4? With 8 CPUs?
>

Will be fixed in v2, thanks.

> I also find it curious that you went through the unusual
> (and IMO confusing) effort to allocate a name to each and
> every SPI in the system, but didn't do it for any on the PPIs...
>

Yeah, after some consideration I removed the whole interrupts header
and used hard-coded values instead. I probably felt it would be right
thing to have, just because there is no public TRM for Exynos850, thus
documenting interrupts somewhere would be nice. But that reasoning is
wrong, as trying to mix that kind of documentation with code just
clutters it. The right thing to do is probably just provide a public
TRM, but that's not for me to decide, alas :) Anyway, will be fixed in
v2.

>
> > +     };
> > +
> > +     timer {
> > +             compatible = "arm,armv8-timer";
> > +             interrupts = <GIC_PPI 13
> > +                             (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +                          <GIC_PPI 14
> > +                             (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +                          <GIC_PPI 11
> > +                             (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +                          <GIC_PPI 10
> > +                             (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> > +             clock-frequency = <26000000>;
>
> No, please. Fix the firmware to program CNTFRQ_EL0 on each
> and every CPU. This isn't 2012 anymore.
>

Ok, will remove that property in v2. Though it looks like CNTFRQ_EL0
register can be only changed in EL3 execution level, so I'll have to
ask the vendor to fix their BL31 or whatever. But that might take some
time, so I'll have to keep "clock-frequency" workaround in my local
tree for now, to make scheduler work.

> You are also missing the hypervisor virtual timer interrupt.
>

Checked SoC TRM, there is no PPI for hypervisor virtual timer
interrupt, and no mentioning of it at all. Likewise, I checked ARMv8
ARM and TRM, almost no description of it. Also, I checked other
platforms, and seems like everyone does the same (having only 4
interrupts). And I wasn't able to find any documentation on that, so I
guess I'll leave it as is, if you don't mind.

> > +             use-clocksource-only;
> > +             use-physical-timer;
>
> Thankfully, these two properties do not exist.
>

Yeah, that's just some leftover from vendor's kernel, overlook by
me... Will remove in v2, thanks.

> Thanks,
>
>          M.
> --
> Jazz is not dead. It just smells funny...