linux-kernel - [PATCH 5/8] arm64: dts: s32g2: add serial/uart support

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Message-ID: <20210805065429.27485-6-clin@suse.com>
Date:   Thu,  5 Aug 2021 14:54:26 +0800
From:   Chester Lin <clin@...e.com>
To:     Rob Herring <robh+dt@...nel.org>
CC:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-serial@...r.kernel.org,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        Oleksij Rempel <linux@...pel-privat.de>,
        Stefan Riedmueller <s.riedmueller@...tec.de>,
        Matthias Schiffer <matthias.schiffer@...tq-group.com>,
        Li Yang <leoyang.li@....com>,
        Fabio Estevam <festevam@...il.com>,
        Matteo Lisi <matteo.lisi@...icam.com>,
        Frieder Schrempf <frieder.schrempf@...tron.de>,
        Tim Harvey <tharvey@...eworks.com>,
        Jagan Teki <jagan@...rulasolutions.com>, s32@....com,
        catalin-dan.udma@....com, bogdan.hamciuc@....com,
        bogdan.folea@....com, ciprianmarian.costea@....com,
        radu-nicolae.pirea@....com, ghennadi.procopciuc@....com,
        Matthias Brugger <matthias.bgg@...il.com>,
        Andreas Färber <afaerber@...e.de>,
        "Ivan T . Ivanov" <iivanov@...e.de>,
        "Lee, Chun-Yi" <jlee@...e.com>, Chester Lin <clin@...e.com>
Subject: [PATCH 5/8] arm64: dts: s32g2: add serial/uart support

Add serial/uart support for NXP S32G2.

Signed-off-by: Chester Lin <clin@...e.com>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 31 ++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 3321819c1a2d..0076eacad8a6 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
+ * Copyright 2017-2020 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -11,6 +12,12 @@ / {
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -82,6 +89,30 @@ soc {
 
 		ranges;
 
+		uart0: serial@...c8000 {
+			compatible = "fsl,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0 0x401c8000 0 0x3000>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
+		uart1: serial@...cc000 {
+			compatible = "fsl,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0 0x401cc000 0 0x3000>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
+		uart2: serial@...bc000 {
+			compatible = "fsl,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0 0x402bc000 0 0x3000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@...00000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
-- 
2.30.0