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Message-ID: <87wnp0b86y.wl-maz@kernel.org>
Date: Thu, 05 Aug 2021 09:35:17 +0100
From: Marc Zyngier <maz@...nel.org>
To: Sunil Muthuswamy <sunilmut@...rosoft.com>
Cc: Robin Murphy <robin.murphy@....com>,
Thomas Gleixner <tglx@...utronix.de>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"catalin.marinas@....com" <catalin.marinas@....com>,
"will@...nel.org" <will@...nel.org>,
Michael Kelley <mikelley@...rosoft.com>,
Boqun Feng <Boqun.Feng@...rosoft.com>,
KY Srinivasan <kys@...rosoft.com>,
Arnd Bergmann <arnd@...db.de>
Subject: Re: [EXTERNAL] Re: [RFC 1/1] irqchip/gic-v3-its: Add irq domain and chip for Direct LPI without ITS
On Wed, 04 Aug 2021 21:10:43 +0100,
Sunil Muthuswamy <sunilmut@...rosoft.com> wrote:
>
> Thanks Marc and Robin for clarifying. I see and understand the point
> about having explicit MSI mappings in the firmware specification for
> Direct LPIs for generic hardware support.
>
> Hey Mark
I assume this is for me?
> would you be willing to consider a scoped down implementation of GIC
> Direct LPI with just an IRQ chip implementation and no Direct LPI
> PCI-MSI IRQ chip.
Could you please clarify? If you are not implementing MSIs, how can a
device signal LPIs? At the end of the day, something has to write into
the RD, and it isn't going to happen by sheer magic.
> This will allow a MSI provider (such as Hyper-V vPCI) to provide a
> PCI-MSI IRQ chip on top of the Direct LPI IRQ chip and enable
> PCI-MSI scenarios, and avoid building in assumptions in other cases
> (like PCI) where firmware specification is not available.
I really don't get what you are suggesting. Could you please describe
what you have in mind?
M.
--
Without deviation from the norm, progress is not possible.
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