linux-kernel - Re: [v8,1/2] dt-bindings: reset: mt8195: add toprgu reset-controller header file

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Message-ID: <daa97d7e-2184-0b1e-3afd-c357b022c966@roeck-us.net>
Date:   Thu, 5 Aug 2021 20:02:31 -0700
From:   Guenter Roeck <linux@...ck-us.net>
To:     Christine Zhu <Christine.Zhu@...iatek.com>, wim@...ux-watchdog.org,
        robh+dt@...nel.org, matthias.bgg@...il.com
Cc:     srv_heupstream@...iatek.com, linux-mediatek@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-watchdog@...r.kernel.org, devicetree@...r.kernel.org,
        seiya.wang@...iatek.com
Subject: Re: [v8,1/2] dt-bindings: reset: mt8195: add toprgu reset-controller
 header file

On 8/5/21 7:36 PM, Christine Zhu wrote:
> Add toprgu reset-controller header file for MT8195 platform.
> 
> Signed-off-by: Christine Zhu <Christine.Zhu@...iatek.com>
> Acked-by: Rob Herring <robh@...nel.org>

Reviewed-by: Guenter Roeck <linux@...ck-us.net>

> ---
>   include/dt-bindings/reset/mt8195-resets.h | 29 +++++++++++++++++++++++
>   1 file changed, 29 insertions(+)
>   create mode 100644 include/dt-bindings/reset/mt8195-resets.h
> 
> diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
> new file mode 100644
> index 000000000000..a26bccc8b957
> --- /dev/null
> +++ b/include/dt-bindings/reset/mt8195-resets.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)*/
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + * Author: Christine Zhu <christine.zhu@...iatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
> +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
> +
> +#define MT8195_TOPRGU_CONN_MCU_SW_RST          0
> +#define MT8195_TOPRGU_INFRA_GRST_SW_RST        1
> +#define MT8195_TOPRGU_APU_SW_RST               2
> +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST     6
> +#define MT8195_TOPRGU_MMSYS_SW_RST             7
> +#define MT8195_TOPRGU_MFG_SW_RST               8
> +#define MT8195_TOPRGU_VENC_SW_RST              9
> +#define MT8195_TOPRGU_VDEC_SW_RST              10
> +#define MT8195_TOPRGU_IMG_SW_RST               11
> +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST        13
> +#define MT8195_TOPRGU_AUDIO_SW_RST             14
> +#define MT8195_TOPRGU_CAMSYS_SW_RST            15
> +#define MT8195_TOPRGU_EDPTX_SW_RST             16
> +#define MT8195_TOPRGU_ADSPSYS_SW_RST           21
> +#define MT8195_TOPRGU_DPTX_SW_RST              22
> +#define MT8195_TOPRGU_SPMI_MST_SW_RST          23
> +
> +#define MT8195_TOPRGU_SW_RST_NUM               16
> +
> +#endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
>