linux-kernel - Re: [PATCH v4 2/5] mmc: sdhci: always obey programmable clock config in preset value

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Message-ID: <YQ6TEhMLXH/4r4BS@qmqm.qmqm.pl>
Date:   Sat, 7 Aug 2021 16:05:06 +0200
From:   Michał Mirosław <mirq-linux@...e.qmqm.pl>
To:     Adrian Hunter <adrian.hunter@...el.com>
Cc:     Kevin Liu <kliu5@...vell.com>,
        Michal Simek <michal.simek@...inx.com>,
        Suneel Garapati <suneel.garapati@...inx.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        Al Cooper <alcooperx@...il.com>
Subject: Re: [PATCH v4 2/5] mmc: sdhci: always obey programmable clock config
 in preset value

On Wed, Aug 04, 2021 at 01:52:21PM +0300, Adrian Hunter wrote:
> On 25/07/21 12:20 pm, Michał Mirosław wrote:
> > When host controller uses programmable clock presets but doesn't
> > advertise programmable clock support, we can only guess what frequency
> > it generates. Let's at least return correct SDHCI_PROG_CLOCK_MODE bit
> > value in this case.
> If the preset value doesn't make sense, why use it at all?

If I understand the spec correctly, when the preset value is used the
values in Clock Control register are ignored by the module and so the
module can also actually use a different clock source than the ones
available to the driver directly. So either way the driver can't be
sure of the exact frequencu used. This is a cleanup to remove a case
when the code ignores a bit's value based on other unspecified assumptions.

[...]
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -1859,11 +1859,14 @@ u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
> >  
> >  			pre_val = sdhci_get_preset_value(host);
> >  			div = FIELD_GET(SDHCI_PRESET_SDCLK_FREQ_MASK, pre_val);
> > -			if (host->clk_mul &&
> > -				(pre_val & SDHCI_PRESET_CLKGEN_SEL)) {
> > +			if (pre_val & SDHCI_PRESET_CLKGEN_SEL) {
> >  				clk = SDHCI_PROG_CLOCK_MODE;
> >  				real_div = div + 1;
> >  				clk_mul = host->clk_mul;
> > +				if (!clk_mul) {
> > +					/* The clock frequency is unknown. Assume undivided base. */
> > +					clk_mul = 1;
> > +				}
> >  			} else {
> >  				real_div = max_t(int, 1, div << 1);
> >  			}