[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <20210807145537.124744-1-xianting.tian@linux.alibaba.com>
Date: Sat, 7 Aug 2021 22:55:37 +0800
From: Xianting Tian <xianting.tian@...ux.alibaba.com>
To: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Xianting Tian <xianting.tian@...ux.alibaba.com>
Subject: [PATCH] riscv: add ARCH_DMA_MINALIGN support
Introduce ARCH_DMA_MINALIGN to riscv arch.
Signed-off-by: Xianting Tian <xianting.tian@...ux.alibaba.com>
---
arch/riscv/include/asm/cache.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
index 9b58b1045..2945bbe2b 100644
--- a/arch/riscv/include/asm/cache.h
+++ b/arch/riscv/include/asm/cache.h
@@ -11,6 +11,8 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
+#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
+
/*
* RISC-V requires the stack pointer to be 16-byte aligned, so ensure that
* the flat loader aligns it accordingly.
--
2.17.1
Powered by blists - more mailing lists