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Message-ID: <YRCzi9tXsUVi5kHS@matsya>
Date: Mon, 9 Aug 2021 10:18:11 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Iskren Chernev <iskren.chernev@...il.com>
Cc: Bjorn Andersson <bjorn.andersson@...aro.org>,
Andy Gross <agross@...nel.org>,
Kishon Vijay Abraham I <kishon@...com>,
Manu Gautam <mgautam@...eaurora.org>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, phone-devel@...r.kernel.org,
~postmarketos/upstreaming@...ts.sr.ht
Subject: Re: [PATCH v1 2/2] phy: qcom-qmp: Add support for SM6115 UFS phy
On 06-08-21, 19:09, Iskren Chernev wrote:
> On 8/6/21 3:57 PM, Vinod Koul wrote:
> > On 05-08-21, 12:17, Iskren Chernev wrote:
> > why are these registers 660 specific and not V3 like we have for
> > other generations..? Quick looks with V3 regs tells me that seem
> > similar....
> >
>
> Well, I looked at them for a long time and the only thing that is similar
> are the first few QSERDES registers from COM_ATB_SEL1=0x000 to
> COM_BIAS_EN_CLKBUFLR_EN=0x034. Everything else is different. So I can re-use
Is the offset different? I thought all Vn registers across chips do have
same offsets..
> the V3 for the similar regs, but they are 10%, so I figured instead of combing
> through all of the sequences to save 10% of the constants and make it slightly
> less readable just use new constants.
>
> Let me know if I should reuse the 14 regs from V3.
reuse yes, but would like to understand more why offsets are different,
Can you point me to downstream code reference for this?
--
~Vinod
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