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Message-ID: <fde88a8a-fd9b-b192-caae-105224d78b47@gmail.com>
Date:   Mon, 9 Aug 2021 13:08:32 +0800
From:   Like Xu <like.xu.linux@...il.com>
To:     Yang Weijiang <weijiang.yang@...el.com>
Cc:     pbonzini@...hat.com, jmattson@...gle.com, seanjc@...gle.com,
        vkuznets@...hat.com, wei.w.wang@...el.com, kvm@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v7 13/15] KVM: x86/vmx: Clear Arch LBREn bit before inject
 #DB to guest

On 6/8/2021 3:42 pm, Yang Weijiang wrote:
> Per ISA spec, need to clear the bit before inject #DB.

Please paste the SDM statement accurately so that the reviewers
can verify that the code is consistent with the documentation.

> 
> Signed-off-by: Yang Weijiang <weijiang.yang@...el.com>
> ---
>   arch/x86/kvm/vmx/vmx.c | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
> 
> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
> index 70314cd93340..31b9c06c9b3b 100644
> --- a/arch/x86/kvm/vmx/vmx.c
> +++ b/arch/x86/kvm/vmx/vmx.c
> @@ -1601,6 +1601,21 @@ static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
>   		vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
>   }
>   
> +static void flip_arch_lbr_ctl(struct kvm_vcpu *vcpu, bool on)
> +{
> +	if (vcpu_to_pmu(vcpu)->event_count > 0 &&

Ugh, this check seems ridiculous/funny to me.

> +	    kvm_cpu_cap_has(X86_FEATURE_ARCH_LBR)) {
> +		u64 lbr_ctl = vmcs_read64(GUEST_IA32_LBR_CTL);
> +
> +		if (on)
> +			lbr_ctl |= 1ULL;
> +		else
> +			lbr_ctl &= ~1ULL;
> +
> +		vmcs_write64(GUEST_IA32_LBR_CTL, lbr_ctl);
> +	}
> +}

...

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