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Date: Tue, 10 Aug 2021 11:29:56 +0530 From: Odelu Kukatla <okukatla@...eaurora.org> To: georgi.djakov@...aro.org, bjorn.andersson@...aro.org, evgreen@...gle.com, Andy Gross <agross@...nel.org>, Rob Herring <robh+dt@...nel.org>, linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Cc: sboyd@...nel.org, mdtipton@...eaurora.org, sibis@...eaurora.org, saravanak@...gle.com, okukatla@...eaurora.org, seansw@....qualcomm.com, elder@...aro.org, linux-pm@...r.kernel.org, linux-arm-msm-owner@...r.kernel.org Subject: [v5 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@...eaurora.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 53a21d0..e78f055 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -586,6 +586,15 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + epss_l3: interconnect@...90000 { + compatible = "qcom,sc7280-epss-l3"; + reg = <0 0x18590000 0 1000>, <0 0x18591000 0 0x100>, + <0 0x18592000 0 0x100>, <0 0x18593000 0 0x100>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + ipa: ipa@...0000 { compatible = "qcom,sc7280-ipa"; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
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