linux-kernel - Re: [PATCH] pinctrl: amd: Fix an issue with shutdown when system set to s0ix

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 11 Aug 2021 10:26:31 +0200
From:   Gabriel C <nix.or.die@...glemail.com>
To:     Mario Limonciello <mario.limonciello@....com>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Raul E Rangel <rrangel@...omium.org>,
        "open list:PIN CONTROL SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>,
        Nehal Shah <Nehal-bakulchandra.Shah@....com>,
        Shyam Sundar S K <Shyam-sundar.S-k@....com>
Subject: Re: [PATCH] pinctrl: amd: Fix an issue with shutdown when system set
 to s0ix

Am Mo., 9. Aug. 2021 um 22:15 Uhr schrieb Mario Limonciello
<mario.limonciello@....com>:
>
> IRQs are getting armed on shutdown causing the system to immediately
> wake back up.
>
> Link: https://lkml.org/lkml/2021/8/2/1114
> Reported-by: nix.or.die@...glemail.com
> CC: Raul E Rangel <rrangel@...omium.org>
> Fixes: d62bd5ce12d7 ("pinctrl: amd: Implement irq_set_wake")
> Signed-off-by: Mario Limonciello <mario.limonciello@....com>
> ---
>  drivers/pinctrl/pinctrl-amd.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
> index a76be6cc26ee..5b764740b829 100644
> --- a/drivers/pinctrl/pinctrl-amd.c
> +++ b/drivers/pinctrl/pinctrl-amd.c
> @@ -444,8 +444,7 @@ static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
>         unsigned long flags;
>         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
>         struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
> -       u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
> -                       BIT(WAKE_CNTRL_OFF_S4);
> +       u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3);
>
>         raw_spin_lock_irqsave(&gpio_dev->lock, flags);
>         pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
> --

Is working fine again with this fix.

Best Regards,

Gabriel C