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Message-ID: <CAK8P3a3ZdZSdiX6_AeSW4qSFhUp+wKrUe6S5z5bKDtcU068sjQ@mail.gmail.com>
Date: Wed, 11 Aug 2021 15:46:23 +0200
From: Arnd Bergmann <arnd@...db.de>
To: Linus Walleij <linus.walleij@...aro.org>
Cc: Piyush Mehta <piyush.mehta@...inx.com>,
Arnd Bergmann <arnd@...db.de>, Zou Wei <zou_wei@...wei.com>,
Greg KH <gregkh@...uxfoundation.org>,
Michal Simek <michal.simek@...inx.com>, wendy.liang@...inx.com,
Nobuhiro Iwamatsu <iwamatsu@...auri.org>,
Bartosz Golaszewski <bgolaszewski@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Rajan Vaja <rajan.vaja@...inx.com>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, git <git@...inx.com>,
Srinivas Goud <sgoud@...inx.com>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V2 1/3] firmware: zynqmp: Add MMIO read and write support
for PS_MODE pin
On Wed, Aug 11, 2021 at 3:08 PM Linus Walleij <linus.walleij@...aro.org> wrote:
>
> On Thu, Aug 5, 2021 at 7:42 PM Piyush Mehta <piyush.mehta@...inx.com> wrote:
>
> > Add Xilinx ZynqMP firmware MMIO APIs support to set and get PS_MODE
> > pins value and status. These APIs create an interface path between
> > mode pin controller driver and low-level API to access GPIO pins.
> >
> > Signed-off-by: Piyush Mehta <piyush.mehta@...inx.com>
> > ---
> > Changes in v2:
> > - Added Xilinx ZynqMP firmware MMIO API support to set and get pin
> > value and status.
>
> I doubt this is "GPIO".
> General Purpose? I think not. It seems to be about boot mode.
Agreed.
> If you need a userspace ABI, then add sysfs files to this firmware
> driver instead of bridging it to the GPIO subsystem.
I don't really want custom user interfaces in firmware drivers either.
What is the high-level description of the 'PS_MODE' here? Is
this perhaps something we already have a user interface for?
Arnd
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