linux-kernel - Re: [PATCH 5/8] arm64: dts: s32g2: add serial/uart support

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Message-ID: <93978882-4b47-4c4a-cd43-60cb5bcdf471@suse.de>
Date:   Thu, 12 Aug 2021 19:42:38 +0200
From:   Andreas Färber <afaerber@...e.de>
To:     Chester Lin <clin@...e.com>, Rob Herring <robh+dt@...nel.org>,
        s32@....com
Cc:     devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-serial@...r.kernel.org,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        Oleksij Rempel <linux@...pel-privat.de>,
        Stefan Riedmueller <s.riedmueller@...tec.de>,
        Matthias Schiffer <matthias.schiffer@...tq-group.com>,
        Li Yang <leoyang.li@....com>,
        Fabio Estevam <festevam@...il.com>,
        Matteo Lisi <matteo.lisi@...icam.com>,
        Frieder Schrempf <frieder.schrempf@...tron.de>,
        Tim Harvey <tharvey@...eworks.com>,
        Jagan Teki <jagan@...rulasolutions.com>,
        catalin-dan.udma@....com, bogdan.hamciuc@....com,
        bogdan.folea@....com, ciprianmarian.costea@....com,
        radu-nicolae.pirea@....com, ghennadi.procopciuc@....com,
        Matthias Brugger <matthias.bgg@...il.com>,
        "Ivan T . Ivanov" <iivanov@...e.de>, "Lee, Chun-Yi" <jlee@...e.com>
Subject: Re: [PATCH 5/8] arm64: dts: s32g2: add serial/uart support

Hi Chester et al.,

On 05.08.21 08:54, Chester Lin wrote:
> Add serial/uart support for NXP S32G2.

You might mention here that (following our initial stub) this commit is
now apparently based on the CodeAurora BSP branch foo (and therefore
adding its last-year copyright below and separate from 4/8).

> 

@NXP: If there are downstream Signed-off-bys that you would like to see
included for this portion here, please speak up.

> Signed-off-by: Chester Lin <clin@...e.com>
> ---
>  arch/arm64/boot/dts/freescale/s32g2.dtsi | 31 ++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 3321819c1a2d..0076eacad8a6 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
>  /*
>   * Copyright (c) 2021 SUSE LLC
> + * Copyright 2017-2020 NXP

@NXP: Should this be updated to include 2021 from your latest BSP
releases? Do you want it visually aligned by adding the ASCII-art?

>   */
>  
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -11,6 +12,12 @@ / {
>  	#address-cells = <2>;
>  	#size-cells = <2>;
>  
> +	aliases {
> +		serial0 = &uart0;
> +		serial1 = &uart1;
> +		serial2 = &uart2;
> +	};

Note: In the past there had been controversies as to whether to define
aliases globally for a SoC or in a .dts specific to a board's usage.
In this case it does not seem to matter much, as uart0 is being used as
console on the reference boards.

> +
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> @@ -82,6 +89,30 @@ soc {
>  
>  		ranges;
>  
> +		uart0: serial@...c8000 {
> +			compatible = "fsl,s32g2-linflexuart",
> +				     "fsl,s32v234-linflexuart";
> +			reg = <0 0x401c8000 0 0x3000>;
> +			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@...cc000 {
> +			compatible = "fsl,s32g2-linflexuart",
> +				     "fsl,s32v234-linflexuart";
> +			reg = <0 0x401cc000 0 0x3000>;
> +			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@...bc000 {
> +			compatible = "fsl,s32g2-linflexuart",
> +				     "fsl,s32v234-linflexuart";
> +			reg = <0 0x402bc000 0 0x3000>;
> +			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
> +			status = "disabled";
> +		};
> +
>  		gic: interrupt-controller@...00000 {
>  			compatible = "arm,gic-v3";
>  			#interrupt-cells = <3>;

Regards,
Andreas

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