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Date: Fri, 13 Aug 2021 16:35:37 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Rob Herring <robh+dt@...nel.org>, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Cc: Alban Bedel <albeu@...e.fr>, Paul Burton <paul.burton@...s.com>,
Oleksij Rempel <o.rempel@...gutronix.de>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Subject: [PATCH] dt-bindings: memory: convert Qualcomm Atheros DDR to dtschema
Convert Qualcomm Atheros AR7xxx/AR9xxx DDR controller to DT schema
format using json-schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
---
.../ath79-ddr-controller.txt | 35 -----------
.../qca,ath79-ddr-controller.yaml | 61 +++++++++++++++++++
2 files changed, 61 insertions(+), 35 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/qca,ath79-ddr-controller.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
deleted file mode 100644
index c81af75bcd88..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
-
-The DDR controller of the AR7xxx and AR9xxx families provides an interface
-to flush the FIFO between various devices and the DDR. This is mainly used
-by the IRQ controller to flush the FIFO before running the interrupt handler
-of such devices.
-
-Required properties:
-
-- compatible: has to be "qca,<soc-type>-ddr-controller",
- "qca,[ar7100|ar7240]-ddr-controller" as fallback.
- On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
- fallback, otherwise "qca,ar7240-ddr-controller" should be used.
-- reg: Base address and size of the controller's memory area
-- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
- the write buffer channel index, should be 1.
-
-Example:
-
- ddr_ctrl: memory-controller@...00000 {
- compatible = "qca,ar9132-ddr-controller",
- "qca,ar7240-ddr-controller";
- reg = <0x18000000 0x100>;
-
- #qca,ddr-wb-channel-cells = <1>;
- };
-
- ...
-
- interrupt-controller {
- ...
- qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
- qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
- <&ddr_ctrl 0>, <&ddr_ctrl 1>;
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/qca,ath79-ddr-controller.yaml b/Documentation/devicetree/bindings/memory-controllers/qca,ath79-ddr-controller.yaml
new file mode 100644
index 000000000000..9566b3421f03
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/qca,ath79-ddr-controller.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/qca,ath79-ddr-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Atheros AR7xxx/AR9xxx DDR controller
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
+
+description: |
+ The DDR controller of the AR7xxx and AR9xxx families provides an interface to
+ flush the FIFO between various devices and the DDR. This is mainly used by
+ the IRQ controller to flush the FIFO before running the interrupt handler of
+ such devices.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: qca,ar9132-ddr-controller
+ - const: qca,ar7240-ddr-controller
+ - items:
+ - enum:
+ - qca,ar7100-ddr-controller
+ - qca,ar7240-ddr-controller
+
+ "#qca,ddr-wb-channel-cells":
+ description: |
+ Specifies the number of cells needed to encode the write buffer channel
+ index.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#qca,ddr-wb-channel-cells"
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ ddr_ctrl: memory-controller@...00000 {
+ compatible = "qca,ar9132-ddr-controller",
+ "qca,ar7240-ddr-controller";
+ reg = <0x18000000 0x100>;
+
+ #qca,ddr-wb-channel-cells = <1>;
+ };
+
+ interrupt-controller {
+ // ...
+ qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
+ qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
+ <&ddr_ctrl 0>, <&ddr_ctrl 1>;
+ };
--
2.30.2
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