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Message-ID: <202108141858.uo8Sgk0q-lkp@intel.com>
Date: Sat, 14 Aug 2021 18:27:07 +0800
From: kernel test robot <lkp@...el.com>
To: Dan Williams <dan.j.williams@...el.com>
Cc: kbuild-all@...ts.01.org,
Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
Ira Weiny <ira.weiny@...el.com>,
Ben Widawsky <ben.widawsky@...el.com>,
Dan Williams <dan.j.williams@...el.com>,
linux-kernel@...r.kernel.org
Subject: [cxl-cxl:pending 34/38] drivers/cxl/acpi.c:185:12: warning: no
previous prototype for 'match_add_root_ports'
tree: https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git pending
head: fa809cc6feedcd2575b63def7135dfaf066266bb
commit: 5885b71419e9e23ff7d404f9c8a8a5c23d42f106 [34/38] tools/testing/cxl: Introduce a mocked-up CXL port hierarchy
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git/commit/?id=5885b71419e9e23ff7d404f9c8a8a5c23d42f106
git remote add cxl-cxl https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git
git fetch --no-tags cxl-cxl pending
git checkout 5885b71419e9e23ff7d404f9c8a8a5c23d42f106
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=ia64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
>> drivers/cxl/acpi.c:185:12: warning: no previous prototype for 'match_add_root_ports' [-Wmissing-prototypes]
185 | __weak int match_add_root_ports(struct pci_dev *pdev, void *data)
| ^~~~~~~~~~~~~~~~~~~~
>> drivers/cxl/acpi.c:236:28: warning: no previous prototype for 'to_cxl_host_bridge' [-Wmissing-prototypes]
236 | __weak struct acpi_device *to_cxl_host_bridge(struct device *host,
| ^~~~~~~~~~~~~~~~~~
vim +/match_add_root_ports +185 drivers/cxl/acpi.c
184
> 185 __weak int match_add_root_ports(struct pci_dev *pdev, void *data)
186 {
187 struct cxl_walk_context *ctx = data;
188 struct pci_bus *root_bus = ctx->root;
189 struct cxl_port *port = ctx->port;
190 int type = pci_pcie_type(pdev);
191 struct device *dev = ctx->dev;
192 u32 lnkcap, port_num;
193 int rc;
194
195 if (pdev->bus != root_bus)
196 return 0;
197 if (!pci_is_pcie(pdev))
198 return 0;
199 if (type != PCI_EXP_TYPE_ROOT_PORT)
200 return 0;
201 if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
202 &lnkcap) != PCIBIOS_SUCCESSFUL)
203 return 0;
204
205 /* TODO walk DVSEC to find component register base */
206 port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
207 rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE);
208 if (rc) {
209 dev_err(dev, "failed to add dport: %s (%d)\n",
210 dev_name(&pdev->dev), rc);
211 ctx->error = rc;
212 return rc;
213 }
214 ctx->count++;
215
216 dev_dbg(dev, "add dport%d: %s\n", port_num, dev_name(&pdev->dev));
217
218 return 0;
219 }
220
221 static struct cxl_dport *find_dport_by_dev(struct cxl_port *port, struct device *dev)
222 {
223 struct cxl_dport *dport;
224
225 device_lock(&port->dev);
226 list_for_each_entry(dport, &port->dports, list)
227 if (dport->dport == dev) {
228 device_unlock(&port->dev);
229 return dport;
230 }
231
232 device_unlock(&port->dev);
233 return NULL;
234 }
235
> 236 __weak struct acpi_device *to_cxl_host_bridge(struct device *host,
237 struct device *dev)
238 {
239 struct acpi_device *adev = to_acpi_device(dev);
240
241 if (strcmp(acpi_device_hid(adev), "ACPI0016") == 0) {
242 dev_dbg(host, "found host bridge %s\n", dev_name(&adev->dev));
243 return adev;
244 }
245 return NULL;
246 }
247
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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