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Message-ID: <YRwDETpe019RFU/q@robh.at.kernel.org>
Date: Tue, 17 Aug 2021 13:42:25 -0500
From: Rob Herring <robh@...nel.org>
To: Sam Protsenko <semen.protsenko@...aro.org>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Linus Walleij <linus.walleij@...aro.org>,
Tomasz Figa <tomasz.figa@...il.com>,
Marc Zyngier <maz@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Jiri Slaby <jirislaby@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Charles Keepax <ckeepax@...nsource.wolfsonmicro.com>,
Ryu Euiyoul <ryu.real@...sung.com>,
Tom Gall <tom.gall@...aro.org>,
Sumit Semwal <sumit.semwal@...aro.org>,
John Stultz <john.stultz@...aro.org>,
Amit Pundir <amit.pundir@...aro.org>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-samsung-soc@...r.kernel.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH v3 7/7] arm64: dts: exynos: Add Exynos850 SoC support
On Wed, Aug 11, 2021 at 02:48:27PM +0300, Sam Protsenko wrote:
> Samsung Exynos850 is ARMv8-based mobile-oriented SoC.
>
> This patch adds minimal SoC support by including next Device Tree nodes:
>
> 1. Octa cores (Cortex-A55), supporting PSCI v1.0
> 2. ARM architecture timer (armv8-timer)
> 3. Interrupt controller (GIC-400)
> 4. Pinctrl nodes for GPIO
> 5. Serial node
>
> Signed-off-by: Sam Protsenko <semen.protsenko@...aro.org>
> ---
> Changes in v3:
> - Used generic fixed clock for serial
>
> Changes in v2:
> * Commit message:
> - Documented added dts features instead of CPU features
>
> * exynos850-usi.dtsi:
> - Removed, moved everything to exynos850.dtsi
>
> * exynos850.dtsi:
> - Root node:
> - Added comment about engineering name (Exynos3830)
> - Renamed pinctrl nodes, adding domain names
> - Used hard coded IRQ numbers instead of named constants everywhere
> - Added soc node, moved next nodes there: gic, clock, pinctrls and
> serial
> - Used address-cells=1 for soc node and removed unneeded 0x0 from
> reg properties
> - Moved exynos850-pinctrl.dtsi include line to the end of
> exynos850.dtsi
> - Coding style fixes
> - cpus:
> - Used address-cells=1 for cpus node
> - Renamed cpu@...1 to cpu@1, and so on
> - Left only "arm,cortex-a55" for cpus compatible
> - Renamed reg = <0x0001> to <0x1> for cpus
> - armv8 timer:
> - Add comment about missing HV timer IRQ to armv8 timer node
> - Removed not existing properties from armv8 timer node
> - Fixed cpu number in CPU_MASK()
> - Removed obsolete clock-frequency property
> - GIC:
> - Fixed GIC type to be GIC-400
> - Fixed size of GIC's 2nd region to be 0x2000
> - serial node:
> - Hard coded clock number for serial_0 for now; will replace with
> named const once proper clock driver is implemented
> - Removed gate_uart_clk0 clock from serial_0, as that clock is not
> supported in serial driver anyway (yet)
> - clock node:
> - Fixed clock controller node name (@0x12.. -> @12..)
>
> * exynos850-pinctrl.dtsi:
> - Referenced pinctrl nodes instead of defining those again in root node
> - Fixed interrupt-cells (3 -> 2)
> - Fixed USI related comments for pin config nodes
> - Removed decon_f_te_* and fm_lna_en nodes (won't be used)
> - Reordered pin config nodes by pin numbers
> - Improved all comments
> - Used existing named constants for pin-function and pin-pud
> - Fixed node names (used hyphens instead of underscore)
> - Fixed warnings found in W=1 build
>
> .../boot/dts/exynos/exynos850-pinctrl.dtsi | 748 ++++++++++++++++++
> arch/arm64/boot/dts/exynos/exynos850.dtsi | 261 ++++++
> 2 files changed, 1009 insertions(+)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos850.dtsi
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> new file mode 100644
> index 000000000000..ba5d5f33e2f6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos850-pinctrl.dtsi
> @@ -0,0 +1,748 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright (C) 2017 Samsung Electronics Co., Ltd.
> + * Copyright (C) 2021 Linaro Ltd.
> + *
> + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device
> + * tree nodes in this file.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/pinctrl/samsung.h>
> +
> +&pinctrl_alive {
> + gpa0: gpa0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + gpa1: gpa1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + gpa2: gpa2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + gpa3: gpa3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + gpa4: gpa4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + gpq0: gpq0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + /* I2C5 (also called CAM_PMIC_I2C in TRM) */
> + i2c5_bus: i2c5-bus {
Please name all the pinctrl nodes with some pattern you can match on
once there is a schema. '-pins$' is my suggestion.
> + samsung,pins = "gpa3-5", "gpa3-6";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
> +
> + /* I2C6 (also called MOTOR_I2C in TRM) */
> + i2c6_bus: i2c6-bus {
> + samsung,pins = "gpa3-7", "gpa4-0";
> + samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
> + samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
> + samsung,pin-drv = <0>;
> + };
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