linux-kernel - Re: [PATCH v1 7/7] ARM: dts: colibri-imx6ull-emmc: add device trees

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Date:   Thu, 19 Aug 2021 16:24:38 +0000
From:   Marcel Ziswiler <marcel.ziswiler@...adex.com>
To:     "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
CC:     "soc@...nel.org" <soc@...nel.org>,
        Max Krummenacher <max.krummenacher@...adex.com>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "linux-imx@....com" <linux-imx@....com>,
        "festevam@...il.com" <festevam@...il.com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "frowand.list@...il.com" <frowand.list@...il.com>,
        "olof@...om.net" <olof@...om.net>, "arnd@...db.de" <arnd@...db.de>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>
Subject: Re: [PATCH v1 7/7] ARM: dts: colibri-imx6ull-emmc: add device trees

On Thu, 2021-08-19 at 16:03 +0200, Marcel Ziswiler wrote:
> From: Max Krummenacher <max.krummenacher@...adex.com>
> 
> Add devices trees for a Colibri iMX6ULL 1GB which has a eMMC instead of
> the raw NAND used on other SKUs.
> 
> Related-to: ELB-4056, ELB-4058
> Signed-off-by: Max Krummenacher <max.krummenacher@...adex.com>
> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@...adex.com>
> 
> ---
> 
>  arch/arm/boot/dts/Makefile                    |   1 +
>  .../boot/dts/imx6ull-colibri-emmc-eval-v3.dts |  17 ++
>  .../dts/imx6ull-colibri-emmc-nonwifi.dtsi     | 185 ++++++++++++++++++
>  arch/arm/boot/dts/imx6ull-colibri.dtsi        |  30 ++-
>  4 files changed, 232 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts
>  create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi
> 
> ...
>
> diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
> index 0cdbf7b6e7285..f432fc0a6a530 100644
> --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: (GPL-2.0 OR MIT)
>  /*
> - * Copyright 2018 Toradex AG
> + * Copyright 2018-2021 Toradex AG
>   */
>  
>  #include "imx6ull.dtsi"
> @@ -345,6 +345,19 @@ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01       0xb0b0 /* SODIMM 63 */
>                 >;
>         };
>  
> +               /*
> +                * With an eMMC instead of a raw NAND device the following pins
> +                * are available at SODIMM pins
> +                */
> +               pinctrl_gpmi_gpio: gpmi-gpio-grp {
> +                       fsl,pins = <
> +                               MX6UL_PAD_NAND_ALE__GPIO4_IO10          0x10b0 /* SODIMM 140 */
> +                               MX6UL_PAD_NAND_CE0_B__GPIO4_IO13        0x10b0 /* SODIMM 144 */
> +                               MX6UL_PAD_NAND_CLE__GPIO4_IO15          0x10b0 /* SODIMM 146 */
> +                               MX6UL_PAD_NAND_READY_B__GPIO4_IO12      0x10b0 /* SODIMM 142 */
> +                       >;
> +               };
> +

Just noticed that I somehow messed up the indentation above with one spurious tab too much. Will correct that
in a v2. Sorry about that.

>         pinctrl_gpmi_nand: gpmi-nand-grp {
>                 fsl,pins = <
>                         MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0x100a9
> @@ -533,6 +546,21 @@ MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT       0x10
>                 >;
>         };
>  
> +               pinctrl_usdhc2emmc: usdhc2emmcgrp {
> +                       fsl,pins = <
> +                               MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
> +                               MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
> +                               MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
> +                               MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
> +                               MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
> +                               MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
> +                               MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
> +                               MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
> +                               MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
> +                               MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
> +                       >;
> +               };
> +

Ditto above.

>         pinctrl_wdog: wdog-grp {
>                 fsl,pins = <
>                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0

Cheers

Marcel