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Message-ID: <d5894435-c5e1-890d-880c-6b6390fe50d8@redhat.com>
Date: Thu, 19 Aug 2021 18:38:57 +0200
From: Paolo Bonzini <pbonzini@...hat.com>
To: Sean Christopherson <seanjc@...gle.com>,
Wei Huang <wei.huang2@....com>
Cc: kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
vkuznets@...hat.com, wanpengli@...cent.com, jmattson@...gle.com,
joro@...tes.org, tglx@...utronix.de, mingo@...hat.com,
bp@...en8.de, x86@...nel.org, hpa@...or.com
Subject: Re: [PATCH v3 3/3] KVM: SVM: Add 5-level page table support for SVM
On 18/08/21 19:32, Sean Christopherson wrote:
> On Wed, Aug 18, 2021, Wei Huang wrote:
>> When the 5-level page table is enabled on host OS, the nested page table
>> for guest VMs must use 5-level as well. Update get_npt_level() function
>> to reflect this requirement. In the meanwhile, remove the code that
>> prevents kvm-amd driver from being loaded when 5-level page table is
>> detected.
>>
>> Signed-off-by: Wei Huang <wei.huang2@....com>
>> Signed-off-by: Paolo Bonzini <pbonzini@...hat.com>
>
> If this patch authored by Paolo, he needs to be attributed via From:. If Paolo
> is a co-author, he needs a Co-developed-by:. If either of those is true, your
> SOB needs to be last in the chain since you are the last handler of the patch.
> If neither is true, Paolo's SOB should be removed.
I didn't even remember writing this, but it's possible I pseudocoded in
an email just like you did below.
>> - return PT64_ROOT_4LEVEL;
>> + bool la57 = (cr4_read_shadow() & X86_CR4_LA57) != 0;
>> +
>> + return la57 ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
>
> Why obfuscate this? KVM is completely hosed if pgtable_l5_enabled() doesn't
> match host CR4. E.g.
>
> return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
That also suggests the above pseudocoding scenario, where I'd be too
lazy to look up the correct spelling of pgtable_l5_enabled().
Paolo
>> #else
>> return PT32E_ROOT_LEVEL;
>> #endif
>> @@ -462,11 +464,6 @@ static int has_svm(void)
>> return 0;
>> }
>>
>> - if (pgtable_l5_enabled()) {
>> - pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n");
>> - return 0;
>> - }
>> -
>> return 1;
>> }
>>
>> --
>> 2.31.1
>>
>
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