linux-kernel - Re: [PATCH v13] phy: HiSilicon: Add driver for Kirin 970 PCIe PHY

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Message-ID: <202108210625.U8TaX1jP-lkp@intel.com>
Date:   Sat, 21 Aug 2021 07:04:01 +0800
From:   kernel test robot <lkp@...el.com>
To:     Mauro Carvalho Chehab <mchehab@...nel.org>,
        Vinod Koul <vkoul@...nel.org>
Cc:     clang-built-linux@...glegroups.com, kbuild-all@...ts.01.org,
        linux-media@...r.kernel.org, linuxarm@...wei.com,
        mauro.chehab@...wei.com,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Manivannan Sadhasivam <mani@...nel.org>,
        Rob Herring <robh@...nel.org>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v13] phy: HiSilicon: Add driver for Kirin 970 PCIe PHY

Hi Mauro,

I love your patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.14-rc6 next-20210820]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Mauro-Carvalho-Chehab/phy-HiSilicon-Add-driver-for-Kirin-970-PCIe-PHY/20210820-214510
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git d992fe5318d8d7af9510b879439a3c7f283da442
config: x86_64-buildonly-randconfig-r002-20210821 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project d9c5613e856cf2addfbf892fc4c1ce9ef9feceaa)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/1cc067fe7e9ca4a45f061447087187d1852fb716
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Mauro-Carvalho-Chehab/phy-HiSilicon-Add-driver-for-Kirin-970-PCIe-PHY/20210820-214510
        git checkout 1cc067fe7e9ca4a45f061447087187d1852fb716
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>

All warnings (new ones prefixed by >>):

>> drivers/phy/hisilicon/phy-hi3670-pcie.c:358:6: warning: variable 'val' is used uninitialized whenever 'if' condition is true [-Wsometimes-uninitialized]
           if (enable) {
               ^~~~~~
   drivers/phy/hisilicon/phy-hi3670-pcie.c:364:12: note: uninitialized use occurs here
                   while (!(val & FNPLL_HAS_LOCKED)) {
                            ^~~
   drivers/phy/hisilicon/phy-hi3670-pcie.c:358:2: note: remove the 'if' if its condition is always false
           if (enable) {
           ^~~~~~~~~~~~~
   drivers/phy/hisilicon/phy-hi3670-pcie.c:355:9: note: initialize the variable 'val' to silence this warning
           u32 val;
                  ^
                   = 0
   1 warning generated.


vim +358 drivers/phy/hisilicon/phy-hi3670-pcie.c

   351	
   352	static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable)
   353	{
   354		struct device *dev = phy->dev;
   355		u32 val;
   356		int time = PLL_CTRL_WAIT_TIME;
   357	
 > 358		if (enable) {
   359			/* pd = 0 */
   360			hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_MMC1PLL_DISABLE,
   361					       SOC_PCIEPHY_MMC1PLL_CTRL16);
   362	
   363			/* choose FNPLL */
   364			while (!(val & FNPLL_HAS_LOCKED)) {
   365				if (!time) {
   366					dev_err(dev, "wait for pll_lock timeout\n");
   367					return -EINVAL;
   368				}
   369				time--;
   370				udelay(1);
   371				val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
   372			}
   373	
   374			hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_PCIEPL_BP,
   375					       SOC_PCIEPHY_MMC1PLL_CTRL20);
   376	
   377		} else {
   378			hi3670_apb_phy_updatel(phy,
   379					       PCIE_PHY_MMC1PLL_DISABLE,
   380					       PCIE_PHY_MMC1PLL_DISABLE,
   381					       SOC_PCIEPHY_MMC1PLL_CTRL16);
   382	
   383			hi3670_apb_phy_updatel(phy, PCIE_PHY_PCIEPL_BP,
   384					       PCIE_PHY_PCIEPL_BP,
   385					       SOC_PCIEPHY_MMC1PLL_CTRL20);
   386		}
   387	
   388		return 0;
   389	}
   390	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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