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Message-ID: <CAE-0n53gsF-U4YwZyVyjXm2_Fw6zc-FObzx1ATC4X_KXSRsJVA@mail.gmail.com>
Date: Thu, 19 Aug 2021 23:44:32 -0700
From: Stephen Boyd <swboyd@...omium.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Doug Anderson <dianders@...omium.org>,
Felipe Balbi <balbi@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Matthias Kaehlcke <mka@...omium.org>,
Rob Herring <robh+dt@...nel.org>,
Sandeep Maheswaram <sanm@...eaurora.org>
Cc: devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-usb@...r.kernel.org, linux-kernel@...r.kernel.org,
Pratham Pratap <prathampratap@...eaurora.org>
Subject: Re: [PATCH v5 2/3] arm64: dts: qcom: sc7280: Add USB related nodes
Quoting Sandeep Maheswaram (2021-08-19 22:34:14)
> On 8/18/2021 1:28 AM, Stephen Boyd wrote:
> > Quoting Sandeep Maheswaram (2021-07-06 06:00:12)
> >> Add nodes for DWC3 USB controller, QMP and HS USB PHYs in sc7280 SOC.
> >>
> >> Signed-off-by: Sandeep Maheswaram <sanm@...eaurora.org>
> >> Reviewed-by: Matthias Kaehlcke <mka@...omium.org>
> >> ---
> >> Changed qmp usb phy to usb dp phy combo node as per Stephen's comments.
> >> Changed dwc to usb and added SC7280 compatible as per Bjorn's comments.
> >>
> >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 164 +++++++++++++++++++++++++++++++++++
> >> 1 file changed, 164 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> index a8c274a..cd6908f 100644
> >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >> @@ -1035,6 +1035,125 @@
> >> };
> >> };
> >>
> > [...]
> >> +
> >> + usb_2: usb@...8800 {
> >> + compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
> >> + reg = <0 0x08cf8800 0 0x400>;
> >> + status = "disabled";
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> + ranges;
> >> + dma-ranges;
> >> +
> >> + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
> >> + <&gcc GCC_USB30_SEC_MASTER_CLK>,
> >> + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
> >> + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> >> + <&gcc GCC_USB30_SEC_SLEEP_CLK>;
> >> + clock-names = "cfg_noc", "core", "iface","mock_utmi",
> >> + "sleep";
> >> +
> >> + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
> >> + <&gcc GCC_USB30_SEC_MASTER_CLK>;
> >> + assigned-clock-rates = <19200000>, <200000000>;
> >> +
> >> + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
> >> + <&pdc 13 IRQ_TYPE_EDGE_RISING>,
> >> + <&pdc 12 IRQ_TYPE_EDGE_RISING>;
> > I'm seeing this cause a warning at boot
> >
> > [ 4.724756] irq: type mismatch, failed to map hwirq-12 for
> > interrupt-controller@...0000!
> > [ 4.733401] irq: type mismatch, failed to map hwirq-13 for
> > interrupt-controller@...0000!
> I should be usingĀ IRQ_TYPE_LEVEL_HIGH. Will correct in next version.
Ok. Please send a patch to fix it as this is already staged to be merged
in the next merge window.
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