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Message-ID: <0ac67f14-b25c-2e3b-fdd9-f5f101d9caad@ti.com>
Date: Fri, 20 Aug 2021 17:01:40 +0530
From: Apurva Nandan <a-nandan@...com>
To: Miquel Raynal <miquel.raynal@...tlin.com>
CC: Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>,
Mark Brown <broonie@...nel.org>,
Patrice Chotard <patrice.chotard@...s.st.com>,
Boris Brezillon <boris.brezillon@...labora.com>,
<linux-mtd@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<linux-spi@...r.kernel.org>, Pratyush Yadav <p.yadav@...com>
Subject: Re: [PATCH 10/13] mtd: spinand: Add octal_dtr_enable() for Winbond
manufacturer_ops
Hi Miquèl,
On 07/08/21 12:36 am, Miquel Raynal wrote:
> Hi Apurva,
>
> Apurva Nandan <a-nandan@...com> wrote on Tue, 13 Jul 2021 13:05:35
> +0000:
>
>> Add implementation of octal_dtr_enable() manufacturer_ops for Winbond.
>> To switch to Ocatl DTR mode, setting programmable dummy cycles and
>> SPI IO mode using the volatile configuration register is required. To
>> function at max 120MHz SPI clock in Octal DTR mode, 12 programmable
>> dummy clock cycle setting is required. (Default number of dummy cycle
>> are 8 clocks)
>>
>> Set the programmable dummy cycle to 12 clocks, and SPI IO mode to
>> Octal DTR with Data Strobe in the VCR. Also, perform a READ ID
>> operation in Octal DTR SPI mode to ensure the switch was successful.
>
> Commit title should contain "winbond:" (same for the previous patch and
> possibly next ones as well).
>
Okay, got it!
>> Datasheet: https://www.winbond.com/export/sites/winbond/datasheet/W35N01JW_Datasheet_Brief.pdf
>>
>> Signed-off-by: Apurva Nandan <a-nandan@...com>
>> ---
>> drivers/mtd/nand/spi/winbond.c | 42 ++++++++++++++++++++++++++++++++++
>> 1 file changed, 42 insertions(+)
>>
>> diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
>> index a7052a9ca171..58cda07c15a0 100644
>> --- a/drivers/mtd/nand/spi/winbond.c
>> +++ b/drivers/mtd/nand/spi/winbond.c
>> @@ -16,6 +16,14 @@
>>
>> #define WINBOND_CFG_BUF_READ BIT(3)
>>
>> +/* Octal DTR SPI mode (8D-8D-8D) with Data Strobe output*/
>> +#define WINBOND_IO_MODE_VCR_OCTAL_DTR 0xE7
>> +#define WINBOND_IO_MODE_VCR_ADDR 0x00
>> +
>> +/* Use 12 dummy clk cycles for using Octal DTR SPI at max 120MHZ */
>> +#define WINBOND_DUMMY_CLK_COUNT 12
>> +#define WINBOND_DUMMY_CLK_VCR_ADDR 0x01
>> +
>> static SPINAND_OP_VARIANTS(read_cache_variants,
>> SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
>> SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
>> @@ -142,8 +150,42 @@ static int winbond_write_vcr_op(struct spinand_device *spinand, u8 reg, u8 val)
>> return 0;
>> }
>>
>> +static int winbond_spinand_octal_dtr_enable(struct spinand_device *spinand)
>> +{
>> + int ret;
>> + struct spi_mem_op op;
>> +
>> + ret = winbond_write_vcr_op(spinand, WINBOND_DUMMY_CLK_VCR_ADDR,
>> + WINBOND_DUMMY_CLK_COUNT);
>> + if (ret)
>> + return ret;
>> +
>> + ret = winbond_write_vcr_op(spinand, WINBOND_IO_MODE_VCR_ADDR,
>> + WINBOND_IO_MODE_VCR_OCTAL_DTR);
>> + if (ret)
>> + return ret;
>> +
>> + /* Read flash ID to make sure the switch was successful. */
>> + op = (struct spi_mem_op)
>> + SPI_MEM_OP(SPI_MEM_OP_CMD_DTR(2, 0x9f9f, 8),
>> + SPI_MEM_OP_NO_ADDR,
>> + SPI_MEM_OP_DUMMY_DTR(16, 8),
>> + SPI_MEM_OP_DATA_IN_DTR(SPINAND_MAX_ID_LEN,
>> + spinand->scratchbuf, 8));
>> +
>> + ret = spi_mem_exec_op(spinand->spimem, &op);
>> + if (ret)
>> + return ret;
>> +
>> + if (memcmp(spinand->scratchbuf, spinand->id.data, SPINAND_MAX_ID_LEN))
>> + return -EINVAL;
>> +
>> + return 0;
>> +}
>> +
>> static const struct spinand_manufacturer_ops winbond_spinand_manuf_ops = {
>> .init = winbond_spinand_init,
>> + .octal_dtr_enable = winbond_spinand_octal_dtr_enable,
>> };
>>
>> const struct spinand_manufacturer winbond_spinand_manufacturer = {
>
>
>
>
> Thanks,
> Miquèl
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>
Thanks,
Apurva Nandan
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