linux-kernel - Re: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL state

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Message-ID: <20210822015035.GB4545@hoboy.vegasvil.org>
Date:   Sat, 21 Aug 2021 18:50:35 -0700
From:   Richard Cochran <richardcochran@...il.com>
To:     "Machnikowski, Maciej" <maciej.machnikowski@...el.com>
Cc:     "Kubalewski, Arkadiusz" <arkadiusz.kubalewski@...el.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "intel-wired-lan@...ts.osuosl.org" <intel-wired-lan@...ts.osuosl.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kselftest@...r.kernel.org" <linux-kselftest@...r.kernel.org>,
        "Brandeburg, Jesse" <jesse.brandeburg@...el.com>,
        "Nguyen, Anthony L" <anthony.l.nguyen@...el.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "shuah@...nel.org" <shuah@...nel.org>,
        "arnd@...db.de" <arnd@...db.de>,
        "nikolay@...dia.com" <nikolay@...dia.com>,
        "cong.wang@...edance.com" <cong.wang@...edance.com>,
        "colin.king@...onical.com" <colin.king@...onical.com>,
        "gustavoars@...nel.org" <gustavoars@...nel.org>,
        "Bross, Kevin" <kevin.bross@...el.com>,
        "Stanton, Kevin B" <kevin.b.stanton@...el.com>,
        Ahmad Byagowi <abyagowi@...com>
Subject: Re: [RFC net-next 1/7] ptp: Add interface for acquiring DPLL state

On Fri, Aug 20, 2021 at 06:30:02PM +0000, Machnikowski, Maciej wrote:

> I did a talk at netDev 0x15 covering SyncE - you can refer to the slides for more detailed info, and hopefully the recording will be available soon as well:
> https://netdevconf.info/0x15/session.html?Introduction-to-time-synchronization-over-Ethernet

These slides are very clear and nicely done!

( And they also confirm that (ab)using the PHC chardev ioctl for the DPLL
stuff is the wrong interface ;^)

> The SyncE capable PHY is a PHY that can recover the physical clock,
> at which the data symbols are transferred, (usually) divide it and
> output it to the external PLL. It can also redirect the recovered
> and divided clock to more than one pin.

Right, and as your slides show so clearly, the DPLL is connected to
the PHY, not to the time stamping unit with the PTP clock.

> Since the 40.5.2 is not applicable to higher-speed ethernet which
> don't use auto-negotiation, but rather the link training sequence
> where the RX side always syncs its clock to the TX side.

I really want an interface that will also work with Gigabit and even
100 Megabit like the PHYTER (which does support SyncE).

> The external DPLL tunes the frequency generated by a crystal to the frequency recovered by the PHY, and drives the outputs.
> 
> On the other end - the SyncE PHY uses the clock generated by the DPLL to transmit the data to the next element.

So I guess that this is an implementation detail of the higher speed PHYs.

> That's why the RFC proposes 2 interfaces:
> - one for enabling redirected clock on a selected pin of the PHY
> - one for the physical frequency lock of the DPLL
> 
> The connection with the PTP subsystem is that in most use cases I
> heard about SyncE is used as a physical frequency syntonization for
> PTP clocks.

As your slides correctly show, SyncE is about distributing frequency
and not about Phase/ToD.  Of course you can combine SyncE with PTP to
get both, provided that you disable frequency adjustment in the PTP
software stack (in linuxptp, this is the "nullf" servo).  But SyncE in
fact predates PTP, and it can and should be configurable even on
interfaces that lack PHC altogther (or on kernels without PHC
enabled).

> Let me know if that makes more sense now. We could add a separate
> SyncE and separate PTP DPLL monitoring interfaces, but in most cases
> they will point to the same device.

This is just a coincidence of the device you are working with.  The
kernel really needs an interface that works with all kind of hardware
setups.  Imagine a computer with discrete MACs with HW time
stamping/PHC and discrete PHYs with SyncE support.  The PHC driver
won't have any connection to the PHY+DPLL.

Your API must be on the interface/MAC, with the possibility being
handled directly by the MAC driver (for integrated devices) or calling
into the PHY layers (phylib, phylink, and drivers/phy).

If you need a DPLL monitoring interface for your card, it ought to go
through the network interface to the MAC/PHY driver and then to the
DPLL itself.  That way, it will work with different types of hardware.

Thanks,
Richard