linux-kernel - [PATCH 0/9] Improve support for AMD SPI controllers

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Message-ID: <20210824104041.708945-1-tanureal@opensource.cirrus.com>
Date:   Tue, 24 Aug 2021 11:40:32 +0100
From:   Lucas Tanure <tanureal@...nsource.cirrus.com>
To:     Mark Brown <broonie@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "Rafael J . Wysocki" <rafael@...nel.org>,
        Sanjay R Mehta <sanju.mehta@....com>,
        Nehal Bakulchandra Shah <Nehal-Bakulchandra.shah@....com>
CC:     <linux-kernel@...r.kernel.org>, <linux-spi@...r.kernel.org>,
        <patches@...nsource.cirrus.com>,
        Lucas Tanure <tanureal@...nsource.cirrus.com>
Subject: [PATCH 0/9] Improve support for AMD SPI controllers

Add support for AMDI0062 and overcome the fact that the
controller can't hold the chip select activated between
transfers.

AMD SPI controller starts the SPI transfer by copying a
special byte called opcode into the bus, followed by the
TX register bytes from the FIFO into the bus.
If the RX register is not zero, it will copy RX bytes
from the bus to the FIFO.

Rules:
 - It must have an opcode set, which can be the first
byte from the writing part
 - The writing part of the FIFO always goes first
 - It's not full duplex, it writes TX bytes and then
reads RX bytes into the FIFO
 - Write and Read share the same FIFO. If the transfer
needs to write N bytes, it will only be able to read
(70 - N) bytes.
 - The chip select can only be activated during that
transaction. If a second transfer rely on the address
written during a previous transfer, it needs to write
an updated address, or it will fail, as the device in
the SPI bus will not understand a read without an
address as the chip select was not held between transfers.

So, when the regmap splits a write to an address or read from
an address into 2 separated transfers inside one message the
AMD SPI driver needs to merge them back into a single one.
Also it needs to be sure that the of bytes to read|write is
a little less so the address can fit into the FIFO.

Lucas Tanure (9):
  regmap: spi: Set regmap max raw r/w from max_transfer_size
  spi: core: Add flag for controllers that can't hold cs between
    transfers
  regmap: spi: SPI_CONTROLLER_CS_PER_TRANSFER affects max read/write
  spi: amd: Refactor code to use less spi_master_get_devdata
  spi: amd: Refactor amd_spi_busy_wait to use readl_poll_timeout
  spi: amd: Remove uneeded variable
  spi: amd: Check for idle bus before execute opcode
  spi: amd: Refactor to overcome 70 bytes per CS limitation
  spi: amd: Add support for latest platform

 drivers/base/regmap/regmap-spi.c |  44 +++-
 drivers/base/regmap/regmap.c     |   9 +
 drivers/spi/spi-amd.c            | 415 ++++++++++++++++++++-----------
 include/linux/regmap.h           |   2 +
 include/linux/spi/spi.h          |   1 +
 5 files changed, 315 insertions(+), 156 deletions(-)

-- 
2.33.0