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Message-ID: <20210825011120.30481-4-chun-jie.chen@mediatek.com>
Date: Wed, 25 Aug 2021 09:11:18 +0800
From: Chun-Jie Chen <chun-jie.chen@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Nicolas Boichat <drinkcat@...omium.org>
CC: <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
<linux-mediatek@...ts.infradead.org>,
<srv_heupstream@...iatek.com>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
Chun-Jie Chen <chun-jie.chen@...iatek.com>
Subject: [v1 3/5] arm64: dts: mediatek: Correct SPI clock of MT8192
update uart0 ~ 7 clocks to the real ones.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@...iatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 48 ++++++++++++------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 31d135e18784..d1c85d3e152b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -355,9 +355,9 @@
#size-cells = <0>;
reg = <0 0x1100a000 0 0x1000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -369,9 +369,9 @@
#size-cells = <0>;
reg = <0 0x11010000 0 0x1000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -383,9 +383,9 @@
#size-cells = <0>;
reg = <0 0x11012000 0 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -397,9 +397,9 @@
#size-cells = <0>;
reg = <0 0x11013000 0 0x1000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI3>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -411,9 +411,9 @@
#size-cells = <0>;
reg = <0 0x11018000 0 0x1000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI4>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -425,9 +425,9 @@
#size-cells = <0>;
reg = <0 0x11019000 0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI5>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -439,9 +439,9 @@
#size-cells = <0>;
reg = <0 0x1101d000 0 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI6>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -453,9 +453,9 @@
#size-cells = <0>;
reg = <0 0x1101e000 0 0x1000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI7>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
--
2.18.0
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