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Message-ID: <CAJZ5v0gjh7k5Zingv06b-bwFG9E+SZysW6GJQA8pwcTsMqEjCw@mail.gmail.com>
Date: Wed, 25 Aug 2021 20:11:04 +0200
From: "Rafael J. Wysocki" <rafael@...nel.org>
To: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
Cc: "Zhang, Rui" <rui.zhang@...el.com>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Viresh Kumar <viresh.kumar@...aro.org>,
Len Brown <lenb@...nel.org>,
Linux PM <linux-pm@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] cpufreq: intel_pstate: Process HWP Guaranteed change notification
On Fri, Aug 20, 2021 at 4:40 AM Srinivas Pandruvada
<srinivas.pandruvada@...ux.intel.com> wrote:
>
> It is possible that HWP guaranteed ratio is changed in response to
> change in power and thermal limits. For example when Intel Speed Select
> performance profile is changed or there is change in TDP, hardware can
> send notifications. It is possible that the guaranteed ratio is
> increased. This creates an issue when turbo is disabled, as the old
> limits set in MSR_HWP_REQUEST are still lower and hardware will clip
> to older limits.
>
> This change enables HWP interrupt and process HWP interrupts. When
> guaranteed is changed, calls cpufreq_update_policy() so that driver
> callbacks are called to update to new HWP limits. This callback
> is called from a delayed workqueue of 10ms to avoid frequent updates.
>
> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>
Applied along with the [1/2] as 5.15 material, thanks!
> ---
> drivers/cpufreq/intel_pstate.c | 39 ++++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c
> index bb4549959b11..0fd2375c1f1e 100644
> --- a/drivers/cpufreq/intel_pstate.c
> +++ b/drivers/cpufreq/intel_pstate.c
> @@ -32,6 +32,7 @@
> #include <asm/cpu_device_id.h>
> #include <asm/cpufeature.h>
> #include <asm/intel-family.h>
> +#include "../drivers/thermal/intel/thermal_interrupt.h"
>
> #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
>
> @@ -219,6 +220,7 @@ struct global_params {
> * @sched_flags: Store scheduler flags for possible cross CPU update
> * @hwp_boost_min: Last HWP boosted min performance
> * @suspended: Whether or not the driver has been suspended.
> + * @hwp_notify_work: workqueue for HWP notifications.
> *
> * This structure stores per CPU instance data for all CPUs.
> */
> @@ -257,6 +259,7 @@ struct cpudata {
> unsigned int sched_flags;
> u32 hwp_boost_min;
> bool suspended;
> + struct delayed_work hwp_notify_work;
> };
>
> static struct cpudata **all_cpu_data;
> @@ -1625,6 +1628,40 @@ static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
>
> /************************** sysfs end ************************/
>
> +static void intel_pstate_notify_work(struct work_struct *work)
> +{
> + mutex_lock(&intel_pstate_driver_lock);
> + cpufreq_update_policy(smp_processor_id());
> + wrmsrl(MSR_HWP_STATUS, 0);
> + mutex_unlock(&intel_pstate_driver_lock);
> +}
> +
> +void notify_hwp_interrupt(void)
> +{
> + unsigned int this_cpu = smp_processor_id();
> + struct cpudata *cpudata;
> + u64 value;
> +
> + if (!hwp_active || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
> + return;
> +
> + rdmsrl(MSR_HWP_STATUS, value);
> + if (!(value & 0x01))
> + return;
> +
> + cpudata = all_cpu_data[this_cpu];
> + schedule_delayed_work_on(this_cpu, &cpudata->hwp_notify_work, msecs_to_jiffies(10));
> +}
> +
> +static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
> +{
> + /* Enable HWP notification interrupt for guaranteed performance change */
> + if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
> + INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
> + wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
> + }
> +}
> +
> static void intel_pstate_hwp_enable(struct cpudata *cpudata)
> {
> /* First disable HWP notification interrupt as we don't process them */
> @@ -1634,6 +1671,8 @@ static void intel_pstate_hwp_enable(struct cpudata *cpudata)
> wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
> if (cpudata->epp_default == -EINVAL)
> cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
> +
> + intel_pstate_enable_hwp_interrupt(cpudata);
> }
>
> static int atom_get_min_pstate(void)
> --
> 2.31.1
>
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