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Message-ID: <CAE-0n53zk0ogf=TUknMoCAPDd97=jq3Czpp6b1c9E29ormuCSQ@mail.gmail.com>
Date: Thu, 26 Aug 2021 07:51:45 +0000
From: Stephen Boyd <swboyd@...omium.org>
To: Sasha Levin <sashal@...nel.org>, sbhanu@...eaurora.org,
stable@...r.kernel.org
Cc: Adrian Hunter <adrian.hunter@...el.com>,
Ulf Hansson <ulf.hansson@...aro.org>,
linux-mmc@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: FAILED: Patch "mmc: sdhci-msm: Update the software timeout value
for sdhc" failed to apply to 5.4-stable tree
Quoting Sasha Levin (2021-08-23 19:57:54)
> The patch below does not apply to the 5.4-stable tree.
> If someone wants it applied there, or to any other stable or longterm
> tree, then please email the backport, including the original git commit
> id to <stable@...r.kernel.org>.
>
It looks like it conflicts with inline crypto code. This is equivalent
and compiles on v5.4.142
------8<-------
>From cd5d41c802f7b3e20c0c0ebd6bf0cb335954fd89 Mon Sep 17 00:00:00 2001
From: Shaik Sajida Bhanu <sbhanu@...eaurora.org>
Date: Fri, 16 Jul 2021 17:16:14 +0530
Subject: [PATCH] mmc: sdhci-msm: Update the software timeout value for sdhc
commit 67b13f3e221ed81b46a657e2b499bf8b20162476 upstream.
Whenever SDHC run at clock rate 50MHZ or below, the hardware data
timeout value will be 21.47secs, which is approx. 22secs and we have
a current software timeout value as 10secs. We have to set software
timeout value more than the hardware data timeout value to avioid seeing
the below register dumps.
[ 332.953670] mmc2: Timeout waiting for hardware interrupt.
[ 332.959608] mmc2: sdhci: ============ SDHCI REGISTER DUMP ===========
[ 332.966450] mmc2: sdhci: Sys addr: 0x00000000 | Version: 0x00007202
[ 332.973256] mmc2: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
[ 332.980054] mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000027
[ 332.986864] mmc2: sdhci: Present: 0x01f801f6 | Host ctl: 0x0000001f
[ 332.993671] mmc2: sdhci: Power: 0x00000001 | Blk gap: 0x00000000
[ 333.000583] mmc2: sdhci: Wake-up: 0x00000000 | Clock: 0x00000007
[ 333.007386] mmc2: sdhci: Timeout: 0x0000000e | Int stat: 0x00000000
[ 333.014182] mmc2: sdhci: Int enab: 0x03ff100b | Sig enab: 0x03ff100b
[ 333.020976] mmc2: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
[ 333.027771] mmc2: sdhci: Caps: 0x322dc8b2 | Caps_1: 0x0000808f
[ 333.034561] mmc2: sdhci: Cmd: 0x0000183a | Max curr: 0x00000000
[ 333.041359] mmc2: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x00000000
[ 333.048157] mmc2: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000
[ 333.054945] mmc2: sdhci: Host ctl2: 0x00000000
[ 333.059657] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr:
0x0000000ffffff218
[ 333.067178] mmc2: sdhci_msm: ----------- VENDOR REGISTER DUMP
-----------
[ 333.074343] mmc2: sdhci_msm: DLL sts: 0x00000000 | DLL cfg:
0x6000642c | DLL cfg2: 0x0020a000
[ 333.083417] mmc2: sdhci_msm: DLL cfg3: 0x00000000 | DLL usr ctl:
0x00000000 | DDR cfg: 0x80040873
[ 333.092850] mmc2: sdhci_msm: Vndr func: 0x00008a9c | Vndr func2 :
0xf88218a8 Vndr func3: 0x02626040
[ 333.102371] mmc2: sdhci: ============================================
So, set software timeout value more than hardware timeout value.
Signed-off-by: Shaik Sajida Bhanu <sbhanu@...eaurora.org>
Acked-by: Adrian Hunter <adrian.hunter@...el.com>
Cc: stable@...r.kernel.org
Link: https://lore.kernel.org/r/1626435974-14462-1-git-send-email-sbhanu@codeaurora.org
Signed-off-by: Ulf Hansson <ulf.hansson@...aro.org>
Signed-off-by: Stephen Boyd <swboyd@...omium.org>
---
drivers/mmc/host/sdhci-msm.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 8bed81cf03ad..8ab963055238 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1589,6 +1589,23 @@ static void sdhci_msm_set_clock(struct
sdhci_host *host, unsigned int clock)
__sdhci_msm_set_clock(host, clock);
}
+static void sdhci_msm_set_timeout(struct sdhci_host *host, struct
mmc_command *cmd)
+{
+ u32 count, start = 15;
+
+ __sdhci_set_timeout(host, cmd);
+ count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL);
+ /*
+ * Update software timeout value if its value is less than hardware data
+ * timeout value. Qcom SoC hardware data timeout value was calculated
+ * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
+ */
+ if (cmd && cmd->data && host->clock > 400000 &&
+ host->clock <= 50000000 &&
+ ((1 << (count + start)) > (10 * host->clock)))
+ host->data_timeout = 22LL * NSEC_PER_SEC;
+}
+
/*
* Platform specific register write functions. This is so that, if any
* register write needs to be followed up by platform specific actions,
@@ -1753,6 +1770,7 @@ static const struct sdhci_ops sdhci_msm_ops = {
.set_uhs_signaling = sdhci_msm_set_uhs_signaling,
.write_w = sdhci_msm_writew,
.write_b = sdhci_msm_writeb,
+ .set_timeout = sdhci_msm_set_timeout,
};
static const struct sdhci_pltfm_data sdhci_msm_pdata = {
--
https://chromeos.dev
> Thanks,
> Sasha
>
> ------------------ original commit in Linus's tree ------------------
>
> From 67b13f3e221ed81b46a657e2b499bf8b20162476 Mon Sep 17 00:00:00 2001
> From: Shaik Sajida Bhanu <sbhanu@...eaurora.org>
> Date: Fri, 16 Jul 2021 17:16:14 +0530
> Subject: [PATCH] mmc: sdhci-msm: Update the software timeout value for sdhc
>
> Whenever SDHC run at clock rate 50MHZ or below, the hardware data
> timeout value will be 21.47secs, which is approx. 22secs and we have
> a current software timeout value as 10secs. We have to set software
> timeout value more than the hardware data timeout value to avioid seeing
> the below register dumps.
>
> [ 332.953670] mmc2: Timeout waiting for hardware interrupt.
> [ 332.959608] mmc2: sdhci: ============ SDHCI REGISTER DUMP ===========
> [ 332.966450] mmc2: sdhci: Sys addr: 0x00000000 | Version: 0x00007202
> [ 332.973256] mmc2: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001
> [ 332.980054] mmc2: sdhci: Argument: 0x00000000 | Trn mode: 0x00000027
> [ 332.986864] mmc2: sdhci: Present: 0x01f801f6 | Host ctl: 0x0000001f
> [ 332.993671] mmc2: sdhci: Power: 0x00000001 | Blk gap: 0x00000000
> [ 333.000583] mmc2: sdhci: Wake-up: 0x00000000 | Clock: 0x00000007
> [ 333.007386] mmc2: sdhci: Timeout: 0x0000000e | Int stat: 0x00000000
> [ 333.014182] mmc2: sdhci: Int enab: 0x03ff100b | Sig enab: 0x03ff100b
> [ 333.020976] mmc2: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000
> [ 333.027771] mmc2: sdhci: Caps: 0x322dc8b2 | Caps_1: 0x0000808f
> [ 333.034561] mmc2: sdhci: Cmd: 0x0000183a | Max curr: 0x00000000
> [ 333.041359] mmc2: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x00000000
> [ 333.048157] mmc2: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000
> [ 333.054945] mmc2: sdhci: Host ctl2: 0x00000000
> [ 333.059657] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr:
> 0x0000000ffffff218
> [ 333.067178] mmc2: sdhci_msm: ----------- VENDOR REGISTER DUMP
> -----------
> [ 333.074343] mmc2: sdhci_msm: DLL sts: 0x00000000 | DLL cfg:
> 0x6000642c | DLL cfg2: 0x0020a000
> [ 333.083417] mmc2: sdhci_msm: DLL cfg3: 0x00000000 | DLL usr ctl:
> 0x00000000 | DDR cfg: 0x80040873
> [ 333.092850] mmc2: sdhci_msm: Vndr func: 0x00008a9c | Vndr func2 :
> 0xf88218a8 Vndr func3: 0x02626040
> [ 333.102371] mmc2: sdhci: ============================================
>
> So, set software timeout value more than hardware timeout value.
>
> Signed-off-by: Shaik Sajida Bhanu <sbhanu@...eaurora.org>
> Acked-by: Adrian Hunter <adrian.hunter@...el.com>
> Cc: stable@...r.kernel.org
> Link: https://lore.kernel.org/r/1626435974-14462-1-git-send-email-sbhanu@codeaurora.org
> Signed-off-by: Ulf Hansson <ulf.hansson@...aro.org>
> ---
> drivers/mmc/host/sdhci-msm.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index e44b7a66b73c..290a14cdc1cf 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -2089,6 +2089,23 @@ static void sdhci_msm_cqe_disable(struct mmc_host *mmc, bool recovery)
> sdhci_cqe_disable(mmc, recovery);
> }
>
> +static void sdhci_msm_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
> +{
> + u32 count, start = 15;
> +
> + __sdhci_set_timeout(host, cmd);
> + count = sdhci_readb(host, SDHCI_TIMEOUT_CONTROL);
> + /*
> + * Update software timeout value if its value is less than hardware data
> + * timeout value. Qcom SoC hardware data timeout value was calculated
> + * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
> + */
> + if (cmd && cmd->data && host->clock > 400000 &&
> + host->clock <= 50000000 &&
> + ((1 << (count + start)) > (10 * host->clock)))
> + host->data_timeout = 22LL * NSEC_PER_SEC;
> +}
> +
> static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
> .enable = sdhci_msm_cqe_enable,
> .disable = sdhci_msm_cqe_disable,
> @@ -2438,6 +2455,7 @@ static const struct sdhci_ops sdhci_msm_ops = {
> .irq = sdhci_msm_cqe_irq,
> .dump_vendor_regs = sdhci_msm_dump_vendor_regs,
> .set_power = sdhci_set_power_noreg,
> + .set_timeout = sdhci_msm_set_timeout,
> };
>
> static const struct sdhci_pltfm_data sdhci_msm_pdata = {
> --
> 2.30.2
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