linux-kernel - Re: [PATCH V6 1/7] arm64: dts: sc7280: Add QSPI node

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Message-ID: <CAE-0n50-9df1riEwcbbS9Dxd5WhKFBKqXAHu-bkwdP4z1NKTWA@mail.gmail.com>
Date:   Thu, 26 Aug 2021 18:02:17 +0000
From:   Stephen Boyd <swboyd@...omium.org>
To:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Rajesh Patil <rajpat@...eaurora.org>,
        Rob Herring <robh+dt@...nel.org>
Cc:     linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, rnayak@...eaurora.org,
        saiprakash.ranjan@...eaurora.org, msavaliy@....qualcomm.com,
        skakit@...eaurora.org, Roja Rani Yarubandi <rojay@...eaurora.org>
Subject: Re: [PATCH V6 1/7] arm64: dts: sc7280: Add QSPI node

Can you please Cc folks who have reviewed prior series when you send
again?

Quoting Rajesh Patil (2021-08-26 06:15:25)
> From: Roja Rani Yarubandi <rojay@...eaurora.org>
>
> Add QSPI DT node and qspi_opp_table for SC7280 SoC.

Might be worth adding here that we put the opp table in / because SPI
nodes assume any child node is a spi device and so we can't put the
table underneath the spi controller.

>
> Signed-off-by: Roja Rani Yarubandi <rojay@...eaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@...eaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 62 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..f8dd5ff 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1318,6 +1337,24 @@
>                         };
>                 };
>
> +               qspi: spi@...c000 {
> +                       compatible = "qcom,qspi-v1";
> +                       reg = <0 0x088dc000 0 0x1000>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
> +                                <&gcc GCC_QSPI_CORE_CLK>;
> +                       clock-names = "iface", "core";
> +                       interconnects = <&gem_noc MASTER_APPSS_PROC 0
> +                                       &cnoc2 SLAVE_QSPI_0 0>;
> +                       interconnect-names = "qspi-config";
> +                       power-domains = <&rpmhpd SC7280_CX>;
> +                       operating-points-v2 = <&qspi_opp_table>;
> +                       status = "disabled";
> +

Nitpick: Drop newline above.

> +               };
> +
>                 dc_noc: interconnect@...0000 {
>                         reg = <0 0x090e0000 0 0x5080>;
>                         compatible = "qcom,sc7280-dc-noc";