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Message-ID: <CAE-0n51YGqp701EzUs1Q1PG89SECVQDdUPsiJ8P95xFj0UFs=A@mail.gmail.com>
Date: Thu, 26 Aug 2021 18:11:34 +0000
From: Stephen Boyd <swboyd@...omium.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rajesh Patil <rajpat@...eaurora.org>,
Rob Herring <robh+dt@...nel.org>
Cc: linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, rnayak@...eaurora.org,
saiprakash.ranjan@...eaurora.org, msavaliy@....qualcomm.com,
skakit@...eaurora.org, Roja Rani Yarubandi <rojay@...eaurora.org>
Subject: Re: [PATCH V6 6/7] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
Quoting Rajesh Patil (2021-08-26 06:15:30)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> index 7c106c0..65126a7 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
> @@ -225,6 +225,10 @@
> status = "okay";
> };
>
> +&qupv3_id_1 {
> + status = "okay";
> +};
> +
Why enable this here but not any of the i2c/spi/uart devices that are a
child? Can this hunk be split off to a different patch?
> &sdhc_1 {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index a3c11b0..32f411f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2040,6 +2469,46 @@
> function = "qup07";
> };
>
> + qup_i2c8_data_clk:qup-i2c8-data-clk {
Unstick please.
> + pins = "gpio32", "gpio33";
> + function = "qup10";
> + };
> +
> + qup_i2c9_data_clk:qup-i2c9-data-clk {
> + pins = "gpio36", "gpio37";
> + function = "qup11";
> + };
> +
> + qup_i2c10_data_clk:qup-i2c10-data-clk {
> + pins = "gpio40", "gpio41";
> + function = "qup12";
> + };
> +
> + qup_i2c11_data_clk:qup-i2c11-data-clk {
> + pins = "gpio44", "gpio45";
> + function = "qup13";
> + };
> +
> + qup_i2c12_data_clk:qup-i2c12-data-clk {
> + pins = "gpio48", "gpio49";
> + function = "qup14";
> + };
> +
> + qup_i2c13_data_clk:qup-i2c13-data-clk {
> + pins = "gpio52", "gpio53";
> + function = "qup15";
> + };
> +
> + qup_i2c14_data_clk:qup-i2c14-data-clk {
> + pins = "gpio56", "gpio57";
> + function = "qup16";
> + };
> +
> + qup_i2c15_data_clk:qup-i2c15-data-clk {
> + pins = "gpio60", "gpio61";
> + function = "qup17";
> + };
All of these.
> +
> qup_spi0_data_clk: qup-spi0-data-clk {
> pins = "gpio0", "gpio1", "gpio2";
> function = "qup00";
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