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Message-ID: <HK0PR06MB3779B6CD28A84D3DC651211191C89@HK0PR06MB3779.apcprd06.prod.outlook.com>
Date:   Fri, 27 Aug 2021 08:49:16 +0000
From:   ChiaWei Wang <chiawei_wang@...eedtech.com>
To:     Joel Stanley <joel@....id.au>
CC:     kernel test robot <lkp@...el.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "andrew@...id.au" <andrew@...id.au>,
        "linux-aspeed@...ts.ozlabs.org" <linux-aspeed@...ts.ozlabs.org>,
        "openbmc@...ts.ozlabs.org" <openbmc@...ts.ozlabs.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kbuild-all@...ts.01.org" <kbuild-all@...ts.01.org>
Subject: RE: [PATCH v3 3/4] soc: aspeed: Add eSPI driver

> From: Joel Stanley <joel@....id.au>
> Sent: Friday, August 27, 2021 1:49 PM
> 
> On Fri, 27 Aug 2021 at 03:52, ChiaWei Wang
> <chiawei_wang@...eedtech.com> wrote:
> >
> > Aspeed 5th and 6th generation SoCs are based on the ARM 32-bits
> architecture.
> > Should we follow the report to make the driver 64-bits compatible?
> > Or revise the driver to use more specific data types?
> 
> Yes, in general it's expected your driver will compile cleanly for 64-bit
> architectures. This helps with testing and static analysis, where CI builds all the
> drivers for x86.

Understood. Will fix the data type issue in the next submission.
Thanks.

Chiawei

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