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Message-Id: <20210828131814.29589-16-konrad.dybcio@somainline.org>
Date: Sat, 28 Aug 2021 15:18:11 +0200
From: Konrad Dybcio <konrad.dybcio@...ainline.org>
To: ~postmarketos/upstreaming@...ts.sr.ht
Cc: martin.botka@...ainline.org,
angelogioacchino.delregno@...ainline.org,
marijn.suijten@...ainline.org, jamipkettunen@...ainline.org,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Rob Herring <robh@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Brown <broonie@...nel.org>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Viresh Kumar <viresh.kumar@...aro.org>,
Sebastian Reichel <sre@...nel.org>,
Sudeep Holla <sudeep.holla@....com>,
Hector Martin <marcan@...can.st>,
Vinod Koul <vkoul@...nel.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
linux-arm-msm@...r.kernel.org
Subject: [PATCH v2 16/18] arm64: dts: qcom: sm6350: Add iommus property to USB1
This is required for us to be able to access the associated registers, which
are (on at least some devices) gated by default.
Signed-off-by: Konrad Dybcio <konrad.dybcio@...ainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index a3a1f0e63ace..95e69d9f8657 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -584,6 +584,7 @@ usb_1_dwc3: dwc3@...0000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x540 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,has-lpm-erratum;
--
2.33.0
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