linux-kernel - Re: [PATCH v2 02/18] arm64: dts: qcom: Add SM6350 device tree

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <e483238e-29ac-b1ef-ed80-d5ffdbca83bf@codeaurora.org>
Date:   Sun, 29 Aug 2021 01:13:48 +0530
From:   Maulik Shah <mkshah@...eaurora.org>
To:     Konrad Dybcio <konrad.dybcio@...ainline.org>,
        ~postmarketos/upstreaming@...ts.sr.ht
Cc:     martin.botka@...ainline.org,
        angelogioacchino.delregno@...ainline.org,
        marijn.suijten@...ainline.org, jamipkettunen@...ainline.org,
        Rob Herring <robh@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Brown <broonie@...nel.org>,
        Jonathan Cameron <Jonathan.Cameron@...wei.com>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        Sebastian Reichel <sre@...nel.org>,
        Sudeep Holla <sudeep.holla@....com>,
        Hector Martin <marcan@...can.st>,
        Vinod Koul <vkoul@...nel.org>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Kees Cook <keescook@...omium.org>,
        Anton Vorontsov <anton@...msg.org>,
        Colin Cross <ccross@...roid.com>,
        Tony Luck <tony.luck@...el.com>, linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v2 02/18] arm64: dts: qcom: Add SM6350 device tree

Hi,

On 8/28/2021 9:52 PM, Konrad Dybcio wrote:
>>> +
>>> +        tcsr_mutex: hwlock@...0000 {
>>> +            compatible = "qcom,tcsr-mutex";
>>> +            reg = <0x0 0x01f40000 0x0 0x40000>;
>>> +            #hwlock-cells = <1>;
>>> +        };
>>> +
>>> +        pdc: interrupt-controller@...0000 {
>>> +            compatible = "qcom,sm6350-pdc", "qcom,pdc";
>>> +            reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
>> The second reg  0x17c000f0 is neither documented nor used in PDC irq chip driver. can you please remove it?
>>
>> Thanks,
>> Maulik
>>
> Wouldn't it make more sense to keep it (like in other PDC-enabled SoCs' device trees) so that there's no
>
> need to add it back when the driver gains support for spi_configure_type (I believe that's what it's used for)?
The second reg in some of the PDC enabled SoCs' went in since it may 
have slipped throgh code reviews when using downstream
patch as is on upstream.
Also the bindings document for PDC is still in txt, so yaml check could 
not catch the extra register which is not documented.

An attempt to add support for spi_configure_type [1] & [2] had 
suggestion either to access second reg via mailbox or
add another level of irqchip hierarchy between PDC to GIC to configure 
SPI type. Unless both [1] and [2] patch can go in as
PDC irqchip driver won't gain support to use it. (using mailbox approch 
will have mailbox driver to access this register and PDC node may 
mention which mailbox to use).

[1] 
https://patchwork.kernel.org/project/linux-arm-msm/patch/1568411962-1022-7-git-send-email-ilina@codeaurora.org/

[2] 
https://patchwork.kernel.org/project/linux-arm-msm/patch/1568411962-1022-8-git-send-email-ilina@codeaurora.org/

Thanks,
Maulik

>
>
> Konrad
>
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation