| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <CAAEAJfB_qZtVpxk8P=26GkZ1j66v+RzzJTqf3UrfMkWNJ1fmFg@mail.gmail.com>
Date: Sun, 29 Aug 2021 17:54:50 -0300
From: Ezequiel Garcia <ezequiel@...guardiasur.com.ar>
To: "yunfei.dong@...iatek.com" <yunfei.dong@...iatek.com>
Cc: Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Alexandre Courbot <acourbot@...omium.org>,
Hans Verkuil <hverkuil-cisco@...all.nl>,
Tzung-Bi Shih <tzungbi@...omium.org>,
Tiffany Lin <tiffany.lin@...iatek.com>,
Andrew-CT Chen <andrew-ct.chen@...iatek.com>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Tomasz Figa <tfiga@...gle.com>,
Hsin-Yi Wang <hsinyi@...omium.org>,
Fritz Koenig <frkoenig@...omium.org>,
Irui Wang <irui.wang@...iatek.com>,
linux-media <linux-media@...r.kernel.org>,
devicetree <devicetree@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
srv_heupstream <srv_heupstream@...iatek.com>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
George Sun <george.sun@...iatek.com>
Subject: Re: [PATCH v5, 13/15] dt-bindings: media: mtk-vcodec: Adds decoder
dt-bindings for mt8192
On Tue, 17 Aug 2021 at 00:52, yunfei.dong@...iatek.com
<yunfei.dong@...iatek.com> wrote:
>
> Hi Laurent,
>
> Thanks for your detail suggestion.
>
> On Wed, 2021-08-11 at 20:59 +0300, Laurent Pinchart wrote:
> > Hi Yunfei,
> >
> > Thank you for the patch.
> >
> > On Wed, Aug 11, 2021 at 10:57:59AM +0800, Yunfei Dong wrote:
> > > Adds decoder dt-bindings for mt8192.
> > >
> > > Signed-off-by: Yunfei Dong <yunfei.dong@...iatek.com>
> > > ---
> > > v5: no changes
> > >
> > > This patch depends on "Mediatek MT8192 clock support"[1].
> > >
> > > The definition of decoder clocks are in mt8192-clk.h, need to
> > > include them in case of build fail [1].
> > >
> > > [1]
> > > https://patchwork.kernel.org/project/linux-mediatek/list/?series=511175
> > > ---
> > > .../media/mediatek,vcodec-comp-decoder.yaml | 172
> > > ++++++++++++++++++
> > > 1 file changed, 172 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/media/mediatek,vcodec-comp-
> > > decoder.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-
> > > decoder.yaml
> > > b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-
> > > decoder.yaml
> > > new file mode 100644
> > > index 000000000000..083c89933917
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-comp-
> > > decoder.yaml
> > > @@ -0,0 +1,172 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > http://devicetree.org/schemas/iommu/mediatek,vcodec-comp-decoder.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Mediatek Video Decode Accelerator With Component
> > > +
> > > +maintainers:
> > > + - Yunfei Dong <yunfei.dong@...iatek.com>
> > > +
> > > +description: |+
> > > + Mediatek Video Decode is the video decode hardware present in
> > > Mediatek
> > > + SoCs which supports high resolution decoding functionalities.
> > > Required
> > > + master and component node.
> >
> > This should explain how the three IP cores relate to each other.
> >
> I will explain it in next patch.
> > > +
> > > +properties:
> > > + compatible:
> > > + oneOf:
> > > + - enum:
> > > + - mediatek,mt8192-vcodec-dec # for lat hardware
> > > + - mediatek,mtk-vcodec-lat # for core hardware
> > > + - mediatek,mtk-vcodec-core
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > + interrupts:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + maxItems: 5
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: vdec-sel
> > > + - const: vdec-soc-vdec
> > > + - const: vdec-soc-lat
> > > + - const: vdec-vdec
> > > + - const: vdec-top
> > > +
> > > + assigned-clocks: true
> > > +
> > > + assigned-clock-parents: true
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + iommus:
> > > + minItems: 1
> > > + maxItems: 32
> > > + description: |
> > > + List of the hardware port in respective IOMMU block for
> > > current Socs.
> > > + Refer to bindings/iommu/mediatek,iommu.yaml.
> > > +
> > > + dma-ranges:
> > > + maxItems: 1
> > > + description: |
> > > + Describes the physical address space of IOMMU maps to
> > > memory.
> > > +
> > > + mediatek,scp:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + maxItems: 1
> > > + description:
> > > + Describes point to scp.
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - iommus
> > > + - dma-ranges
> > > +
> > > +allOf:
> > > + - if: #master node
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - mediatek,mt8192-vcodec-dec # for lat hardware
> > > +
> > > + then:
> > > + required:
> > > + - mediatek,scp
> > > +
> > > + - if: #component node
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - mediatek,mtk-vcodec-lat # for core hardware
> > > + - mediatek,mtk-vcodec-core
> > > +
> > > + then:
> > > + required:
> > > + - interrupts
> > > + - clocks
> > > + - clock-names
> > > + - assigned-clocks
> > > + - assigned-clock-parents
> > > + - power-domains
> > > +
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > + #include <dt-bindings/memory/mt8192-larb-port.h>
> > > + #include <dt-bindings/interrupt-controller/irq.h>
> > > + #include <dt-bindings/clock/mt8192-clk.h>
> > > + #include <dt-bindings/power/mt8192-power.h>
> > > +
> > > + vcodec_dec: vcodec_dec@...00000 {
> > > + compatible = "mediatek,mt8192-vcodec-dec";
> > > + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
> > > + mediatek,scp = <&scp>;
> > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> > > + };
> > > +
> > > + vcodec_lat: vcodec_lat@...6010000 {
> > > + compatible = "mediatek,mtk-vcodec-lat";
> > > + reg = <0 0x16010000 0 0x800>; /* VDEC_MISC */
> > > + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > > + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > > + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> > > + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> > > + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> > > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
> > > + "vdec-vdec", "vdec-top";
> > > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> > > + };
> > > +
> > > + vcodec_core: vcodec_core@...6025000 {
> > > + compatible = "mediatek,mtk-vcodec-core";
> > > + reg = <0 0x16025000 0 0x1000>; /*
> > > VDEC_CORE_MISC */
> > > + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > > + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys CLK_VDEC_VDEC>,
> > > + <&vdecsys CLK_VDEC_LAT>,
> > > + <&vdecsys CLK_VDEC_LARB1>,
> > > + <&topckgen CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "vdec-sel", "vdec-soc-vdec", "vdec-soc-lat",
> > > + "vdec-vdec", "vdec-top";
> > > + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> > > + };
> >
> > I'm a bit late in the game, reviewing v5 only, but I'm wondering if
> > those IP cores need to be modelled in separate nodes. It would be
> > much
> > easier, from a software point of view, to have a single node, with
> > multiple register ranges.
> >
> > Are some of those IP cores used in different SoCs, combined in
> > different
> > ways, that make a modular design better ?
> >
> Different platform has different hardware, for mt8192 only has three
> nodes. but mt8195 will has five nodes. and the clk/power/irq/iommu are
> different. It is not easy to manage all hardware at the same time in
> one node, need to enable different hardware at the same time, the logic
> will be very complex.
> It is much easier to handle different hardware using component, enable
> different hardware when we need it.
>
>
You can still have one device-tree node for each device, which means
you can still manage your resources (clk/power/irq/iommu) easily, but doing
this so that it avoids an async framework to pull the parts together.
I gave you this feedback several times, and you have been objecting it
every time without even trying to consider a different approach.
Thanks,
Ezequiel
Powered by blists - more mailing lists