lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <163021465232.2676726.1524959516246529010@swboyd.mtv.corp.google.com>
Date:   Sat, 28 Aug 2021 22:24:12 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Sergio Paracuellos <sergio.paracuellos@...il.com>,
        linux-clk@...r.kernel.org
Cc:     mturquette@...libre.com, matthias.bgg@...il.com,
        linux-kernel@...r.kernel.org, dqfext@...il.com
Subject: Re: [PATCH] clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates

Quoting Sergio Paracuellos (2021-07-26 22:55:37)
> 'clk_init_data' for gates is setting up 'CLK_IS_CRITICAL'
> flag for all of them. This was being doing because some
> drivers of this SoC might not be ready to use the clock
> and we don't wanted the kernel to disable them since default
> behaviour without clock driver was to set all gate bits to
> enabled state. After a bit more testing and checking driver
> code it is safe to remove this flag and just let the kernel
> to disable those gates that are not in use. No regressions
> seems to appear.
> 
> Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@...il.com>
> ---

Applied to clk-next

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ