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Message-ID: <20210831034924.86-1-yuzenghui@huawei.com>
Date: Tue, 31 Aug 2021 11:49:24 +0800
From: Zenghui Yu <yuzenghui@...wei.com>
To: <devicetree@...r.kernel.org>, <robh+dt@...nel.org>
CC: <dri-devel@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>,
<airlied@...ux.ie>, <daniel@...ll.ch>,
<wanghaibin.wang@...wei.com>, "Zenghui Yu" <yuzenghui@...wei.com>,
Arnd Bergmann <arnd@...db.de>, Jun Nie <jun.nie@...aro.org>,
Shawn Guo <shawnguo@...nel.org>
Subject: [PATCH] dt-bindings: display: remove zte,vou.txt binding doc
The zte zx platform was removed in commit 89d4f98ae90d ("ARM: remove zte
zx platform") and the zxdrm driver is going to be removed in v5.15 via
drm tree. Let's remove the now obsolete binding doc.
Cc: Arnd Bergmann <arnd@...db.de>
Cc: Jun Nie <jun.nie@...aro.org>
Cc: Shawn Guo <shawnguo@...nel.org>
Signed-off-by: Zenghui Yu <yuzenghui@...wei.com>
---
.../devicetree/bindings/display/zte,vou.txt | 120 ------------------
1 file changed, 120 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/zte,vou.txt
diff --git a/Documentation/devicetree/bindings/display/zte,vou.txt b/Documentation/devicetree/bindings/display/zte,vou.txt
deleted file mode 100644
index 38476475fd60..000000000000
--- a/Documentation/devicetree/bindings/display/zte,vou.txt
+++ /dev/null
@@ -1,120 +0,0 @@
-ZTE VOU Display Controller
-
-This is a display controller found on ZTE ZX296718 SoC. It includes multiple
-Graphic Layer (GL) and Video Layer (VL), two Mixers/Channels, and a few blocks
-handling scaling, color space conversion etc. VOU also integrates the support
-for typical output devices, like HDMI, TV Encoder, VGA, and RGB LCD.
-
-* Master VOU node
-
-It must be the parent node of all the sub-device nodes.
-
-Required properties:
- - compatible: should be "zte,zx296718-vou"
- - #address-cells: should be <1>
- - #size-cells: should be <1>
- - ranges: list of address translations between VOU and sub-devices
-
-* VOU DPC device
-
-Required properties:
- - compatible: should be "zte,zx296718-dpc"
- - reg: Physical base address and length of DPC register regions, one for each
- entry in 'reg-names'
- - reg-names: The names of register regions. The following regions are required:
- "osd"
- "timing_ctrl"
- "dtrc"
- "vou_ctrl"
- "otfppu"
- - interrupts: VOU DPC interrupt number to CPU
- - clocks: A list of phandle + clock-specifier pairs, one for each entry
- in 'clock-names'
- - clock-names: A list of clock names. The following clocks are required:
- "aclk"
- "ppu_wclk"
- "main_wclk"
- "aux_wclk"
-
-* HDMI output device
-
-Required properties:
- - compatible: should be "zte,zx296718-hdmi"
- - reg: Physical base address and length of the HDMI device IO region
- - interrupts : HDMI interrupt number to CPU
- - clocks: A list of phandle + clock-specifier pairs, one for each entry
- in 'clock-names'
- - clock-names: A list of clock names. The following clocks are required:
- "osc_cec"
- "osc_clk"
- "xclk"
-
-* TV Encoder output device
-
-Required properties:
- - compatible: should be "zte,zx296718-tvenc"
- - reg: Physical base address and length of the TVENC device IO region
- - zte,tvenc-power-control: the phandle to SYSCTRL block followed by two
- integer cells. The first cell is the offset of SYSCTRL register used
- to control TV Encoder DAC power, and the second cell is the bit mask.
-
-* VGA output device
-
-Required properties:
- - compatible: should be "zte,zx296718-vga"
- - reg: Physical base address and length of the VGA device IO region
- - interrupts : VGA interrupt number to CPU
- - clocks: Phandle with clock-specifier pointing to VGA I2C clock.
- - clock-names: Must be "i2c_wclk".
- - zte,vga-power-control: the phandle to SYSCTRL block followed by two
- integer cells. The first cell is the offset of SYSCTRL register used
- to control VGA DAC power, and the second cell is the bit mask.
-
-Example:
-
-vou: vou@...0000 {
- compatible = "zte,zx296718-vou";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1440000 0x10000>;
-
- dpc: dpc@0 {
- compatible = "zte,zx296718-dpc";
- reg = <0x0000 0x1000>, <0x1000 0x1000>,
- <0x5000 0x1000>, <0x6000 0x1000>,
- <0xa000 0x1000>;
- reg-names = "osd", "timing_ctrl",
- "dtrc", "vou_ctrl",
- "otfppu";
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topcrm VOU_ACLK>, <&topcrm VOU_PPU_WCLK>,
- <&topcrm VOU_MAIN_WCLK>, <&topcrm VOU_AUX_WCLK>;
- clock-names = "aclk", "ppu_wclk",
- "main_wclk", "aux_wclk";
- };
-
- vga: vga@...0 {
- compatible = "zte,zx296718-vga";
- reg = <0x8000 0x1000>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&topcrm VGA_I2C_WCLK>;
- clock-names = "i2c_wclk";
- zte,vga-power-control = <&sysctrl 0x170 0xe0>;
- };
-
- hdmi: hdmi@...0 {
- compatible = "zte,zx296718-hdmi";
- reg = <0xc000 0x4000>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
- clocks = <&topcrm HDMI_OSC_CEC>,
- <&topcrm HDMI_OSC_CLK>,
- <&topcrm HDMI_XCLK>;
- clock-names = "osc_cec", "osc_clk", "xclk";
- };
-
- tvenc: tvenc@...0 {
- compatible = "zte,zx296718-tvenc";
- reg = <0x2000 0x1000>;
- zte,tvenc-power-control = <&sysctrl 0x170 0x10>;
- };
-};
--
2.19.1
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