linux-kernel - [tip: perf/core] perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints

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Message-ID: <163041166071.25758.13557631748713413002.tip-bot2@tip-bot2>
Date:   Tue, 31 Aug 2021 12:07:40 -0000
From:   "tip-bot2 for Kan Liang" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Kan Liang <kan.liang@...ux.intel.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>, x86@...nel.org,
        linux-kernel@...r.kernel.org
Subject: [tip: perf/core] perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     4034fb207e302cc0b1f304084d379640c1fb1436
Gitweb:        https://git.kernel.org/tip/4034fb207e302cc0b1f304084d379640c1fb1436
Author:        Kan Liang <kan.liang@...ux.intel.com>
AuthorDate:    Thu, 26 Aug 2021 08:32:43 -07:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Tue, 31 Aug 2021 13:59:37 +02:00

perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints

SPR M3UPI have the exact same event constraints as ICX, so add the
constraints.

Fixes: 2a8e51eae7c8 ("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com
---
 arch/x86/events/intel/uncore_snbep.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index cd53057..eb2c6ce 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -5776,6 +5776,7 @@ static struct intel_uncore_type spr_uncore_upi = {
 static struct intel_uncore_type spr_uncore_m3upi = {
 	SPR_UNCORE_PCI_COMMON_FORMAT(),
 	.name			= "m3upi",
+	.constraints		= icx_uncore_m3upi_constraints,
 };
 
 static struct intel_uncore_type spr_uncore_mdf = {