[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20210831134013.1625527-3-michael@walle.cc>
Date: Tue, 31 Aug 2021 15:40:08 +0200
From: Michael Walle <michael@...le.cc>
To: linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Shawn Guo <shawnguo@...nel.org>, Li Yang <leoyang.li@....com>,
Rob Herring <robh+dt@...nel.org>,
Vladimir Oltean <vladimir.oltean@....com>,
Michael Walle <michael@...le.cc>
Subject: [PATCH 2/7] arm64: dts: ls1028a: move Mali DP500 node into /soc
Move it inside the /soc subnode because it is part of the CCSR space.
Signed-off-by: Michael Walle <michael@...le.cc>
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 41 ++++++++++---------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 9a65a7118faa..92e4f004c1c2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -793,6 +793,27 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
+ malidp0: display@...0000 {
+ compatible = "arm,mali-dp500";
+ reg = <0x0 0xf080000 0x0 0x10000>;
+ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+ <0 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "DE", "SE";
+ clocks = <&dpclk>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>,
+ <&clockgen QORIQ_CLK_HWACCEL 2>;
+ clock-names = "pxlclk", "mclk", "aclk", "pclk";
+ arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+ arm,malidp-arqos-value = <0xd000d000>;
+
+ port {
+ dpi0_out: endpoint {
+
+ };
+ };
+ };
+
sai1: audio-controller@...0000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
@@ -1139,24 +1160,4 @@ ftm_alarm0: timer@...0000 {
};
};
- malidp0: display@...0000 {
- compatible = "arm,mali-dp500";
- reg = <0x0 0xf080000 0x0 0x10000>;
- interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
- <0 223 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "DE", "SE";
- clocks = <&dpclk>,
- <&clockgen QORIQ_CLK_HWACCEL 2>,
- <&clockgen QORIQ_CLK_HWACCEL 2>,
- <&clockgen QORIQ_CLK_HWACCEL 2>;
- clock-names = "pxlclk", "mclk", "aclk", "pclk";
- arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
- arm,malidp-arqos-value = <0xd000d000>;
-
- port {
- dp0_out: endpoint {
-
- };
- };
- };
};
--
2.30.2
Powered by blists - more mailing lists