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Message-ID: <70676288-731f-fc14-42bb-c955efc64c57@linaro.org>
Date:   Fri, 3 Sep 2021 01:18:48 +0300
From:   Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To:     Sireesh Kodali <sireeshkodali1@...il.com>
Cc:     phone-devel@...r.kernel.org, ~postmarketos/upstreaming@...ts.sr.ht,
        dri-devel@...ts.freedesktop.org, airlied@...ux.ie,
        robdclark@...il.com, linux-arm-msm@...r.kernel.org,
        Vladimir Lypak <vladimir.lypak@...il.com>,
        Sean Paul <sean@...rly.run>, Daniel Vetter <daniel@...ll.ch>,
        Rob Herring <robh+dt@...nel.org>,
        Abhinav Kumar <abhinavk@...eaurora.org>,
        Jonathan Marek <jonathan@...ek.ca>,
        Rajeev Nandan <rajeevny@...eaurora.org>,
        Krishna Manikandan <mkrishn@...eaurora.org>,
        "open list:DRM DRIVER FOR MSM ADRENO GPU" 
        <freedreno@...ts.freedesktop.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/2] drm/msm/dsi: Add phy configuration for MSM8953

On 02/09/2021 18:59, Sireesh Kodali wrote:
> From: Vladimir Lypak <vladimir.lypak@...il.com>
> 
> Add phy configuration for 14nm dsi phy found on MSM8953 SoC. Only
> difference from existing configurations are io_start addresses.
> 
> Signed-off-by: Vladimir Lypak <vladimir.lypak@...il.com>
> Signed-off-by: Sireesh Kodali <sireeshkodali1@...il.com>
> ---
>   .../bindings/display/msm/dsi-phy-14nm.yaml    |  1 +
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.c         |  2 ++
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy.h         |  1 +
>   drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c    | 21 +++++++++++++++++++
>   4 files changed, 25 insertions(+)

Please split dt-bindings to a separate patch, to be acked by Rob Herring.

After that, the dsi/phy/* part is:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>

> 
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> index 72a00cce0147..7527fb299caa 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> @@ -17,6 +17,7 @@ properties:
>       oneOf:
>         - const: qcom,dsi-phy-14nm
>         - const: qcom,dsi-phy-14nm-660
> +      - const: qcom,dsi-phy-14nm-8953
>   
>     reg:
>       items:
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> index 8c65ef6968ca..9842e04b5858 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> @@ -627,6 +627,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
>   	  .data = &dsi_phy_14nm_cfgs },
>   	{ .compatible = "qcom,dsi-phy-14nm-660",
>   	  .data = &dsi_phy_14nm_660_cfgs },
> +	{ .compatible = "qcom,dsi-phy-14nm-8953",
> +	  .data = &dsi_phy_14nm_8953_cfgs },
>   #endif
>   #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
>   	{ .compatible = "qcom,dsi-phy-10nm",
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> index b91303ada74f..4c8257581bfc 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> @@ -48,6 +48,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs;
> +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
>   extern const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs;
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> index d13552b2213b..9a6b1f0cbbaf 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
> @@ -1065,3 +1065,24 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = {
>   	.io_start = { 0xc994400, 0xc996000 },
>   	.num_dsi_phy = 2,
>   };
> +
> +const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = {
> +	.has_phy_lane = true,
> +	.reg_cfg = {
> +		.num = 1,
> +		.regs = {
> +			{"vcca", 17000, 32},
> +		},
> +	},
> +	.ops = {
> +		.enable = dsi_14nm_phy_enable,
> +		.disable = dsi_14nm_phy_disable,
> +		.pll_init = dsi_pll_14nm_init,
> +		.save_pll_state = dsi_14nm_pll_save_state,
> +		.restore_pll_state = dsi_14nm_pll_restore_state,
> +	},
> +	.min_pll_rate = VCO_MIN_RATE,
> +	.max_pll_rate = VCO_MAX_RATE,
> +	.io_start = { 0x1a94400, 0x1a96400 },
> +	.num_dsi_phy = 2,
> +};
> 


-- 
With best wishes
Dmitry

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