lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <YTJOU/oVWSdxD1uz@google.com>
Date:   Fri, 3 Sep 2021 09:33:23 -0700
From:   Matthias Kaehlcke <mka@...omium.org>
To:     Rajesh Patil <rajpat@...eaurora.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, rnayak@...eaurora.org,
        saiprakash.ranjan@...eaurora.org, msavaliy@....qualcomm.com,
        skakit@...eaurora.org, sboyd@...nel.org, dianders@...omium.org,
        Roja Rani Yarubandi <rojay@...eaurora.org>
Subject: Re: [PATCH V7 3/7] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes

On Fri, Sep 03, 2021 at 09:58:56AM +0530, Rajesh Patil wrote:
> From: Roja Rani Yarubandi <rojay@...eaurora.org>
> 
> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
> 
> Signed-off-by: Roja Rani Yarubandi <rojay@...eaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@...eaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 684 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 682 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 7ec9871..5c6a1d7 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>
> ...
>
> +			qup_spi0_data_clk: qup-spi0-data-clk {
> +				pins = "gpio0", "gpio1", "gpio2";
> +				function = "qup00";
> +			};
> +
> +			qup_spi0_cs: qup-spi0-cs {
> +				pins = "gpio3";
> +				function = "qup00";
> +			};


I think we still want this for all SPI ports, which existed in previous
versions:

			qup_spi0_cs_gpio: qup-spi0-cs-gpio {
				pins = "gpio3";
				function = "gpio";
			};

It just shouldn't be selected together with 'qup_spiN_cs'.

Maybe a follow up patch would be good enough, so:

Reviewed-by: Matthias Kaehlcke <mka@...omium.org>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ