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Message-ID: <CAE-0n51WBdLoJRPs9tWZgdAukJMnkD3V00o7xNYVX77-eToKvw@mail.gmail.com>
Date: Fri, 3 Sep 2021 15:06:02 -0400
From: Stephen Boyd <swboyd@...omium.org>
To: Andy Gross <agross@...nel.org>,
Odelu Kukatla <okukatla@...eaurora.org>,
Rob Herring <robh+dt@...nel.org>, bjorn.andersson@...aro.org,
devicetree@...r.kernel.org, evgreen@...gle.com,
georgi.djakov@...aro.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: mdtipton@...eaurora.org, sibis@...eaurora.org,
saravanak@...gle.com, seansw@....qualcomm.com, elder@...aro.org,
linux-pm@...r.kernel.org, linux-arm-msm-owner@...r.kernel.org
Subject: Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
Quoting Odelu Kukatla (2021-08-20 04:23:41)
> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280
> SoCs.
>
> Signed-off-by: Odelu Kukatla <okukatla@...eaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..cf59b47 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1848,6 +1848,17 @@
> };
> };
>
> + epss_l3: interconnect@...90000 {
> + compatible = "qcom,sc7280-epss-l3";
> + reg = <0 0x18590000 0 1000>,
Is this supposed to be 0x1000?
> + <0 0x18591000 0 0x100>,
> + <0 0x18592000 0 0x100>,
> + <0 0x18593000 0 0x100>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> + #interconnect-cells = <1>;
> + };
> +
> cpufreq_hw: cpufreq@...91000 {
> compatible = "qcom,cpufreq-epss";
> reg = <0 0x18591100 0 0x900>,
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
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