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Date: Sat, 4 Sep 2021 12:19:30 +0530 From: Kajol Jain <kjain@...ux.ibm.com> To: mpe@...erman.id.au, linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org, peterz@...radead.org, mingo@...hat.com, acme@...nel.org, jolsa@...nel.org, namhyung@...nel.org, linux-perf-users@...r.kernel.org, ak@...ux.intel.com Cc: maddy@...ux.ibm.com, atrajeev@...ux.vnet.ibm.com, kjain@...ux.ibm.com, rnsastry@...ux.ibm.com, yao.jin@...ux.intel.com, ast@...nel.org, daniel@...earbox.net, songliubraving@...com, kan.liang@...ux.intel.com, mark.rutland@....com, alexander.shishkin@...ux.intel.com, paulus@...ba.org Subject: [PATCH 1/3] perf: Add macros to specify onchip L2/L3 accesses Add couple of new macros to represent onchip L2 and onchip L3 accesses. Signed-off-by: Kajol Jain <kjain@...ux.ibm.com> --- include/uapi/linux/perf_event.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index f92880a15645..030b3e990ac3 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -1265,7 +1265,9 @@ union perf_mem_data_src { #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ -/* 5-0xa available */ +#define PERF_MEM_LVLNUM_OC_L2 0x05 /* On Chip L2 */ +#define PERF_MEM_LVLNUM_OC_L3 0x06 /* On Chip L3 */ +/* 7-0xa available */ #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ -- 2.26.2
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