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Message-ID: <CAPDyKFrv9HM9y1zgPj6x2K84cPuYXOqaQYqtvKZ51itPtt3ghw@mail.gmail.com>
Date: Tue, 7 Sep 2021 16:34:02 +0200
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: Stephen Boyd <sboyd@...nel.org>, Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Jonathan Marek <jonathan@...ek.ca>,
Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Taniya Das <tdas@...eaurora.org>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<linux-arm-msm@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@...r.kernel.org>,
"Bryan O'Donoghue" <bryan.odonoghue@...aro.org>,
Mark Brown <broonie@...nel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v6 0/6] clk: qcom: use power-domain for sm8250's clock controllers
On Sun, 29 Aug 2021 at 17:54, Dmitry Baryshkov
<dmitry.baryshkov@...aro.org> wrote:
>
> On Sun, 29 Aug 2021 at 06:51, Stephen Boyd <sboyd@...nel.org> wrote:
> >
> > Quoting Dmitry Baryshkov (2021-08-26 14:56:23)
> > > On 26/08/2021 21:31, Stephen Boyd wrote:
> > > > Quoting Dmitry Baryshkov (2021-07-27 13:19:56)
> > > >> On SM8250 both the display and video clock controllers are powered up by
> > > >> the MMCX power domain. Handle this by linking clock controllers to the
> > > >> proper power domain, and using runtime power management to enable and
> > > >> disable the MMCX power domain.
> > > >>
> > > >> Dependencies:
> > > >> - https://lore.kernel.org/linux-arm-msm/20210703005416.2668319-1-bjorn.andersson@linaro.org/
> > > >> (pending)
> > > >
> > > > Does this patch series need to go through the qcom tree? Presumably the
> > > > dependency is going through qcom -> arm-soc
> > >
> > > It looks like Bjorn did not apply his patches in the for-5.15 series, so
> > > we'd have to wait anyway. Probably I should rebase these patches instead
> > > on Rajendra's required-opps patch (which is going in this window).
> > >
> >
> > Ok. Thanks. I'll drop it from my queue for now.
>
> Just for the reference. I've sent v7 of this patchset. After thinking
> more about power domains relationship, I think we have a hole in the
> abstraction here. Currently subdomains cause power domains to be
> powered up, but do not dictate the performance level the parent domain
> should be working in.
That's not entirely true. In genpd_add_subdomain() we verify that if
the child is powered on, the parent must already be powered on,
otherwise we treat this a bad setup and return an error code.
What seems to be missing though, is that if there is a performance
state applied for the child domain, that should be propagated to the
parent domain too. Right?
> While this does not look like an issue for the
> gdsc (and thus it can be easily solved by the Bjorn's patches, which
> enforce rpmhpd to be powered on to 'at least lowest possible'
> performance state, this might be not the case for the future links. I
> think at some point the pd_add_subdomain() interface should be
> extended with the ability to specify minimum required performance
> state when the link becomes on.
I guess that minimum performance state could be considered as a
"required-opp" in the DT node for the power-domain provider, no?
Another option would simply be to manage this solely in the
platform/soc specific genpd provider. Would that work?
> Until that time I have changed code to
> enforce having clock controller in pm resume state when gdsc is
> enabled, thus CC itself votes on parent's (rpmhpd) performance state.
>
>
> --
> With best wishes
> Dmitry
Kind regards
Uffe
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