linux-kernel - Re: [PATCH][next] drm/amdgpu: sdma: clean up identation

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Message-ID: <CADnq5_Psv9HG5C=9OwaXY64uRLnmJ4NjnsbviG6zwvpdmuNcRA@mail.gmail.com>
Date:   Tue, 7 Sep 2021 12:59:02 -0400
From:   Alex Deucher <alexdeucher@...il.com>
To:     Christian König <christian.koenig@....com>
Cc:     Colin King <colin.king@...onical.com>,
        Alex Deucher <alexander.deucher@....com>,
        xinhui pan <Xinhui.Pan@....com>,
        David Airlie <airlied@...ux.ie>,
        Daniel Vetter <daniel@...ll.ch>,
        amd-gfx list <amd-gfx@...ts.freedesktop.org>,
        Maling list - DRI developers 
        <dri-devel@...ts.freedesktop.org>, kernel-janitors@...r.kernel.org,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH][next] drm/amdgpu: sdma: clean up identation

Applied.  Thanks!

Alex

On Fri, Sep 3, 2021 at 2:31 AM Christian König <christian.koenig@....com> wrote:
>
> Am 02.09.21 um 23:51 schrieb Colin King:
> > From: Colin Ian King <colin.king@...onical.com>
> >
> > There is a statement that is indented incorrectly. Clean it up.
> >
> > Signed-off-by: Colin Ian King <colin.king@...onical.com>
>
> Reviewed-by: Christian König <christian.koenig@....com>
>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 ++++----
> >   1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > index 779f5c911e11..e4a96e7e386d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> > @@ -375,10 +375,10 @@ static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
> >    */
> >   static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
> >   {
> > -    uint32_t gcr_cntl =
> > -                 SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
> > -                     SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> > -                     SDMA_GCR_GLI_INV(1);
> > +     uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
> > +                         SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
> > +                         SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
> > +                         SDMA_GCR_GLI_INV(1);
> >
> >       /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
> >       amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
>